Double-fault tolerant architecture design for digital adder

Abstract

In the era of deep sub-micron technology, probability of chip failure has been increased with increase in chip density. A system must be fault tolerant to decrease the failure rate and increase the reliability of it. Multiple faults can affect a system simultaneously and there is a trade-off between area overhead and number of faults tolerated. This paper presents fault tolerant architecture design for a ripple carry adder and a conditional sum adder as fast adder assuming single and double faults. The philosophy can be generalized for any other system which has structural regularity within it.