{"title":"Cuckoo Search Optimizer based Piecewise Gamma Corrected Auto-clipped Tile-wise Equalization for Satellite Image Enhancement","authors":"Himanshu Singh, Anil Kumar, L. Balyan","doi":"10.1109/INDICON.2017.8487901","DOIUrl":"https://doi.org/10.1109/INDICON.2017.8487901","url":null,"abstract":"An efficient optimally weighted framework for piecewise gamma corrected adaptively clipped sectional equalization for overall quality improvement of remotely sensed dark satellite images, is proposed here. In association with it, cuckoo search based biologically inspired optimizer is employed here due to its remarkably attractive exploration and exploitation policies. Tile-wise equalization and associated optimal clipping leads to adaptively equalized interim intensity channel. Piecewise gamma correction using reciprocal gamma values those are derived optimally. Entire allowable intensity span must be exploited so that the count of the void bins can be reduced and hence, cost function is framed by introducing this void-bin count as a penalty term along with desired assurance for entropy as well as contrast enhancement. Rigorous experimentation is executed by employing the performance evaluation and comparison with pre-existing recently proposed and highly appreciated quality enhancement approaches.","PeriodicalId":263943,"journal":{"name":"2017 14th IEEE India Council International Conference (INDICON)","volume":"4 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116822398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Selection of Switching Skills of the Power MOSFET in the Static Converter","authors":"T. Halder","doi":"10.1109/INDICON.2017.8487540","DOIUrl":"https://doi.org/10.1109/INDICON.2017.8487540","url":null,"abstract":"The paper addresses that the performance of the static converter circuit has an impact on the switching techniques (i.e. hard or the soft switching) in terms of the tight regulations, wider range of the input voltage and load applications. The compactness, power density and profile of the power converter system make certain for the high switching frequency operations. The wider compassions are pinpointed between hard and the soft switching skills to enrich the integral performance of the static converter for the cost effective solution of the SMPS technology so the choice of the power MOSFET in the converter circuit is far better than other semiconductors.","PeriodicalId":263943,"journal":{"name":"2017 14th IEEE India Council International Conference (INDICON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129245273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Hybrid-Bridge Asymmetrical Transformerless Five-Level Photovoltaic Inverter","authors":"K. Kumar, A. Kirubakaran, N. Subrahmanyam","doi":"10.1109/INDICON.2017.8488019","DOIUrl":"https://doi.org/10.1109/INDICON.2017.8488019","url":null,"abstract":"This paper presents a new Hybrid-bridge asymmetrical transformerless five-level photovoltaic(PV) inverter and also addresses the behavior of common mode voltage(CMV) and their modulation scheme. The proposed inverter topology is derived from the combination of half-bridge and diode-clamped module, which shall be able to produce less variations in the total CMV and suppress the leakage current as per the DIN VDE 0126 1–1 standards. This can be done through an asymmetrical filter inductor introduced between the inverter and loads. Moreover, the losses due to switching and conduction are less because of the lower voltage stress and reduced switching count which results in higher efficiency of operation. The voltage/current THD of the proposed five-level PV inverter is also within the standard limits. To realize the operation of the five-level inverter output voltage, CMV and leakage current measurement the simulation work is performed in Matlab software and their results are presented.","PeriodicalId":263943,"journal":{"name":"2017 14th IEEE India Council International Conference (INDICON)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124596468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Performance Optimization of ZnO based Thin Film Transistor for Future Generation Display Technology","authors":"A. Singh, V.V. Kharche, P. Chakrabarti","doi":"10.1109/INDICON.2017.8487751","DOIUrl":"https://doi.org/10.1109/INDICON.2017.8487751","url":null,"abstract":"Zinc oxide based thin-film transistors (TFT) built with an Al2O3insulator layer have been analyzed on Silvaco ATLAS™ 2D simulator in order to optimize their performance for application in display systems. We have optimized the geometry of the structure by varying the oxide thickness and semiconductor channel for achieving high performance switching application in display technology. The study revealed that the device can be successfully optimized to achieve a very high value of on-off ratio of $sim 2.78times 10^{8}$ to provide a better driving capability and yet maintaining a low sub-threshold voltage of 0.55 V/decade ensuring high speed of operation. The high performance ZnO based device proposed to be built on Al2O3insulator will make it cost-effective for large display systems.","PeriodicalId":263943,"journal":{"name":"2017 14th IEEE India Council International Conference (INDICON)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130345998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Review on Three-Phase PLLs for Grid Integration of Renewable Energy Sources","authors":"Vivek Khatana, R. Bhimasingu","doi":"10.1109/INDICON.2017.8488071","DOIUrl":"https://doi.org/10.1109/INDICON.2017.8488071","url":null,"abstract":"The developments in the field of Renewable Energy Sources (RES) and a rising environmental concern over the use of conventional sources of energy clubbed together have led to the advent of the distributed sources of energy in the Power Generation and Distribution Systems. Such an integration need to be coherent. RES should ride through any grid disturbances successfully and work in synchronism with the utility grid. This requires the phase angle information apart from the utility voltage magnitude. Phase locked loops (PLLs) is such a technique for estimating the synchronisation information. Various developments have happened in the PLL schemes since it was first used for grid-tie applications. This paper aims to provide a comprehensive review on the use of three-phase PLLs for grid synchronization purposes. A test system based review of the various PLL schemes is done for working under various utility grid conditions. The paper also provides a comparison between different PLLs which can be very helpful as a reference for engineers, and can provide useful insights to academic researchers.","PeriodicalId":263943,"journal":{"name":"2017 14th IEEE India Council International Conference (INDICON)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121516639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Loss of Alertness under Cognitive Fatigue Using EEG Synchronization","authors":"A. Sengupta, Abhishek Tiwari, A. Routray","doi":"10.1109/INDICON.2017.8487619","DOIUrl":"https://doi.org/10.1109/INDICON.2017.8487619","url":null,"abstract":"A drop in alertness is likely to be induced by continuous and repetitive performance of cognitive tasks. EEG has been identified as a significant marker of changes in alertness during performance of a repeated task set. The present paper analyses the drop in alertness of subjects due to increase in fatigue levels using the variation in parameters of brain networks formed from synchronization values of EEG recorded during the performance of an Auditory Response Test. The results show the efficacy of using EEG records to reflect rise in fatigue levels of subjects with increase in cognitive loading.","PeriodicalId":263943,"journal":{"name":"2017 14th IEEE India Council International Conference (INDICON)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121577260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Parallel-prefix modulo adders: A Review","authors":"Shaheen Khan, Z. Jaffery","doi":"10.1109/INDICON.2017.8487570","DOIUrl":"https://doi.org/10.1109/INDICON.2017.8487570","url":null,"abstract":"This brief presents study of some of the most state-of-the-art parallel-prefix modulo adders. Various techniques of parallel-prefix modulo addition like, Ladner-Fischer (LF), Kogge-Stone (KS) and ELM are implemented for general carry recurrence. While another variant of LF is tried for Ling signals. These adders are implemented in ASIC 28/32 nm library saed32hvt_ff0p85v25c for modulo $mathbf{m}=9, 11, 13, 15$ (i.e. $mathbf{n}=4$ bits based on $mathbf{n}=lceillog_{2} m rceil$) and $mathbf{m}=19, 29 (mathbf{n}=5$ bits) for hardware sharing. Performance comparison is carried out in terms of basic area, delay and power metrics. It is observed that ELM, LF and KS mod adders easily outperforms LF using Ling signals adder.","PeriodicalId":263943,"journal":{"name":"2017 14th IEEE India Council International Conference (INDICON)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113975346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analysis of adverse effects due to zeros in non-minimum phase discrete-time linear systems","authors":"Soumyadeep Bose, Y. V. Hote, Sandeep D. Hanwate","doi":"10.1109/INDICON.2017.8487995","DOIUrl":"https://doi.org/10.1109/INDICON.2017.8487995","url":null,"abstract":"In this paper, adverse effects of zeros in non-minimum phase discrete-time systems are analyzed, and methods to detect these effects are presented. The effects such as zero-crossings, overshoot (due to zeros), and initial undershoot, are discussed and mathematically defined. The main advantage of using these methods is this, that the detection can be done using transfer function only, without obtaining the step response. In addition to the discussion on the methods, three different examples of non-minimum phase discrete-time systems are analyzed using these methods. The results are verified by illustrating the corresponding step responses, with zero-order hold. Moreover, one practical non-minimum phase system: DC-DC boost converter, is taken in discrete form and analyzed using the methods so defined.","PeriodicalId":263943,"journal":{"name":"2017 14th IEEE India Council International Conference (INDICON)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124526694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Crosstalk Suppression using Trench-assisted Technique in 9-core Homogeneous Multi Core Fiber","authors":"Dablu Kumar, Rakesh Ranjan","doi":"10.1109/INDICON.2017.8487586","DOIUrl":"https://doi.org/10.1109/INDICON.2017.8487586","url":null,"abstract":"Design and analysis of homogeneous 9-Core Multi core fiber has been done, which is arranged in outer circular ring with eight cores and one core at center. Crosstalk impact has been studied on both outer cores as well as center core, considering 100 km long distance communication. The Crosstalk behaviors with fiber bending radius, wavelength and core-pitch have been investigated analytically. The simulation results illustrate that the crosstalk levels in the proposed 9-core MCF have been reduced remarkably much less than − 50 dB by creating trench around the fiber cores. The relative crosstalk reduction amount has been achieved up to 74 dB by using trench assisted technique.","PeriodicalId":263943,"journal":{"name":"2017 14th IEEE India Council International Conference (INDICON)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127668219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analysis and Design of Sliding Mode Control for MPPT Based PV System with a Battery Storage","authors":"Shalini Marripudi, S. Gudey, G. Gujju","doi":"10.1109/INDICON.2017.8487481","DOIUrl":"https://doi.org/10.1109/INDICON.2017.8487481","url":null,"abstract":"There is a lot of demand of PV systems nowadays. It is due to the fact that they generate power without effecting the surroundings by direct conversion of sun energy into electric power. The advanced topology comprises of a Boost Converter, which boosts up the PV voltage to a value which generates the required single phase AC output voltage of 230V (RMS), 50Hz from the inverter. The output of the step-up converter is cascaded using a single-phase inverter which generates an electric energy of required magnitude and frequency. Perturb and Observe MPPT algorithm is used to obtain maximum power in a PV system. To accumulate the energy, a battery is placed between the inverter and the converter. Depending on the nature of the PV cell and its characteristics, this work designs an SMC to realize the desired inverter output voltage. The work emphasizes on analyzing system stability through a state space model and designing the Sliding Mode Controller. The performance of the controller is verified through effective tracking obtain the desired output voltage response of 230V (RMS). Stability studies are derived through frequency response characteristics. The controller is studied for both dynamic and non-linear nature of the load. The output voltage Total Harmonic Distortion (THD) is found to be consistent with the IEEE 519 standards. The proposed topology is designed for standalone applications. In PSCAD 4.6 version, simulations are performed.","PeriodicalId":263943,"journal":{"name":"2017 14th IEEE India Council International Conference (INDICON)","volume":"22 6S 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115942781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}