{"title":"Development of an industrial real-time system using high level design techniques","authors":"A. Crookell, Innes Ritchie","doi":"10.1109/EMWRTS.1996.557835","DOIUrl":"https://doi.org/10.1109/EMWRTS.1996.557835","url":null,"abstract":"The software for a new industrial quality control instrument requiring real-time control systems has been developed using a hybrid methodology based round integration of different methods. The paper describes the methodology which draws together design theories and techniques from object oriented analysis and design (OOAD), from the PARSE methodology, and from the client-server behaviour modelling. This approach has been applied to the design of the new system which has been implemented and successfully installed on a number of customer sites.","PeriodicalId":262733,"journal":{"name":"Proceedings of the Eighth Euromicro Workshop on Real-Time Systems","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128231179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Leppälä, J. Korhonen, P. Ruuska, J. Toivanen, H. Päivike
{"title":"Real-time approach for development of scientific space instrument software","authors":"K. Leppälä, J. Korhonen, P. Ruuska, J. Toivanen, H. Päivike","doi":"10.1109/EMWRTS.1996.557844","DOIUrl":"https://doi.org/10.1109/EMWRTS.1996.557844","url":null,"abstract":"The paper summarises experience from development of on-board software for three scientific space instruments. Two alternative development philosophies were considered. The obvious approach is to focus on the scientific functions of the instrument, and then interface the program to the \"hardware\" by ad hoc means. An alternative approach was suggested by our experience on industrial applications: considering the software from the real-time point of view. This approach was selected. The paper describes central issues of space instrument software development in the framework of real-time programming. We generalise the real-time approach to cover all issues related with the environment: timing of software functions' execution, support for the project life cycle, and the instrument autonomy concept. We highlight the importance of real time kernel and its extensions as the vehicle for environmental adoption.","PeriodicalId":262733,"journal":{"name":"Proceedings of the Eighth Euromicro Workshop on Real-Time Systems","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130803552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multi-staged discrete loops for real-time systems","authors":"R. Lieger, Johann Blieberger","doi":"10.1109/EMWRTS.1996.557943","DOIUrl":"https://doi.org/10.1109/EMWRTS.1996.557943","url":null,"abstract":"In this paper multi-staged discrete loops are introduced to narrow the gap between for-loops and general loops. Although multi-staged discrete loops can be used in situations that would otherwise require general loops it is still possible to determine the maximum number of iterations, which is trivial for for-loops but extremely difficult for general loops. Thus multi-staged discrete loops form an excellent framework for determining the worst-case performance of a program.","PeriodicalId":262733,"journal":{"name":"Proceedings of the Eighth Euromicro Workshop on Real-Time Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131342136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A generic FSM interpreter for embedded systems","authors":"Juha Viskari, Risto Jokinen, K. Hakkarainen","doi":"10.1109/EMWRTS.1996.557942","DOIUrl":"https://doi.org/10.1109/EMWRTS.1996.557942","url":null,"abstract":"Finite state machines are a fundamental data processing concept especially in specifying the behavioral logic of different embedded control system components. The traditional implementation approach by coding the FSMs is tedious when there is much need for changes, every separately made change leading to a hardware component update. Also the coded FSMs require lots of expensive ROM memory. To overcome these problems we have designed an architecture that is based on interpretable FSMs. The idea is to isolate the behavior behind a separate interpreter process that communicates with the rest of the system through suitable interface processes. These interfaces take care of mapping the logical entities defined to their physical correspondents, while the behavioral logic is taken care of by the interpreted FSMs exclusively. This article presents the architecture and demonstrates the use of interpretable FSMs.","PeriodicalId":262733,"journal":{"name":"Proceedings of the Eighth Euromicro Workshop on Real-Time Systems","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125829182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Real-time kernel in hardware RTU: a step towards deterministic and high-performance real-time systems","authors":"J. Adomat, Johan Furunäs, L. Lindh, Johan Stärner","doi":"10.1109/EMWRTS.1996.557849","DOIUrl":"https://doi.org/10.1109/EMWRTS.1996.557849","url":null,"abstract":"Demands on real-time kernels increase every year: as applications grow larger and become more complex, real-time kernels must give short and predictable response. The RTU is a real-time kernel coprocessor implemented in an ASIC, which is intended to meet the growing expectations on real-time kernels. Since the RTU gives fast response times, it is necessary to define a detailed time-model to improve the understanding of the real-time kernel behaviour in the /spl mu/S-domain. In this paper, we describe how to use the RTU in a single-or multi-processor architecture and a time-model for a RTU based real-time system is defined. The time-model is considered with regards to determinism and performance.","PeriodicalId":262733,"journal":{"name":"Proceedings of the Eighth Euromicro Workshop on Real-Time Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125673728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Barnes, G. Blair, Abderrahmane Lakas, A. Chetwynd
{"title":"Costing-extending the locative logic model of networks","authors":"N. Barnes, G. Blair, Abderrahmane Lakas, A. Chetwynd","doi":"10.1109/EMWRTS.1996.557823","DOIUrl":"https://doi.org/10.1109/EMWRTS.1996.557823","url":null,"abstract":"The paper presents a framework for evaluating the comparative use of system resources in message communication, building on the framework of Locative Temporal Logic (M.J. Wieczorek, 1994) by adding \"costs\" either to the underlying graph representing the communications network of the system in question, or to the messages/actions of the system. This is intended to aid the specification of distributed systems which have to communicate many different types of data, for example multimedia distributed systems. This framework is intended to define requirements. With further refinement of the specifications, the architecture and then an implementation could be derived from the specifications. The specifications can be validated either by simulation with an appropriate tool or by formal proof of correctness of the specifications. The specifications are derived from the description of an application (even a very abstract specification of an application).","PeriodicalId":262733,"journal":{"name":"Proceedings of the Eighth Euromicro Workshop on Real-Time Systems","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132186773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"ERTL: an extension to RTL for the specification, analysis and verification of hybrid systems","authors":"Jon G. Hall, R. Lemos","doi":"10.1109/EMWRTS.1996.557781","DOIUrl":"https://doi.org/10.1109/EMWRTS.1996.557781","url":null,"abstract":"Real time logic (RTL) was introduced as a formalism for reasoning about the relative and absolute timing properties of computational tasks of discrete real-time systems. Extended real time logic (ERTL) is a formalism for the modelling and analysis of relative and absolute timing properties of hybrid systems (systems that combine continuous variables and discrete event dynamics). The extensions provided by ERTL enable the modelling of system behaviour ranging from activities of the physical entities that form part of the environment of a computing system, to the temporal ordering of the computational tasks of the computing system itself thus providing a formal notation that can be used in all stages of software development.","PeriodicalId":262733,"journal":{"name":"Proceedings of the Eighth Euromicro Workshop on Real-Time Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130744651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A communication protocol for hard and soft real-time systems","authors":"C. Eriksson, Henrik Thane, Mikael Gustafsson","doi":"10.1109/EMWRTS.1996.557878","DOIUrl":"https://doi.org/10.1109/EMWRTS.1996.557878","url":null,"abstract":"The distributed real-time community is mainly divided into two camps: hard real-time and soft real-time; hybrid systems have been considered but not to any great extent. In this paper we propose a hybrid communication protocol, which forms a foundation for interconnection of nodes in a distributed hybrid real-time system. The protocol will enable both hard and soft real-time frames on a broadcast communication bus, yet still guarantees the hard real-time behaviour. The protocol will utilise the communication bandwidth more efficiently, which is relevant to cost-sensitive embedded applications.","PeriodicalId":262733,"journal":{"name":"Proceedings of the Eighth Euromicro Workshop on Real-Time Systems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128325076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tae-Young Choe, Chan-Ik Park, Chan-Mo Park, Byung-Seop Kim
{"title":"An improved multi-priority preemptive scheduler for transputer-based real-time systems","authors":"Tae-Young Choe, Chan-Ik Park, Chan-Mo Park, Byung-Seop Kim","doi":"10.1109/EMWRTS.1996.557854","DOIUrl":"https://doi.org/10.1109/EMWRTS.1996.557854","url":null,"abstract":"Real-time applications require an efficient scheduler supporting multiple priority levels and fast preemption. In this paper, we propose a scheduler based on the hardware-supported scheduler of transputers. Though the hardware-supported scheduler of transputers is very efficient in terms of scheduling overhead, it should be extended to support multiple priority levels and fast preemption in order to be used in real-time applications. Many schedulers have been proposed. However, they have several drawbacks in terms of scheduling overhead, preemption latency, and portability. In a previous paper (1990), the authors we have proposed a scheduler featuring low scheduling overhead and portability while suffering from a long preemption delay. In this paper, we propose an improved scheduler which greatly reduces preemption delay by using ISL (Interrupt Save Location) in transputers. Experimental results show that the improved scheduler overhead is about 13.54 /spl mu/sec and its preemption delay is well below 42 /spl mu/sec.","PeriodicalId":262733,"journal":{"name":"Proceedings of the Eighth Euromicro Workshop on Real-Time Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122417053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Peter T. Breuer, N. M. Madrid, L. Sánchez, Andrés Marín López, C. D. Kloos
{"title":"A formal method for specification and refinement of real-time systems","authors":"Peter T. Breuer, N. M. Madrid, L. Sánchez, Andrés Marín López, C. D. Kloos","doi":"10.1109/EMWRTS.1996.557891","DOIUrl":"https://doi.org/10.1109/EMWRTS.1996.557891","url":null,"abstract":"A new formal method for the specification, of real-time system requirements and their refinement to a design architecture is set out here. This integrated method is derived from a recently developed formal semantics, logic and refinement calculus for the IEEE standard hardware specification language VHDL. The specification format consists of three-phase \"before, during and after\" logical schemas, and comes with a combinatorial schema calculus and a refinement theory. The look and feel is reminiscent of Z and VDM and is intended to present an \"upgrade path\" to real-time for users with specification skills in these languages.","PeriodicalId":262733,"journal":{"name":"Proceedings of the Eighth Euromicro Workshop on Real-Time Systems","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115353461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}