17th International Conference on VLSI Design. Proceedings.最新文献

{"title":"Energy model based macrocell placement for wirelength minimization","authors":"S. Alupoaei, S. Katkoori","doi":"10.1109/ICVD.2004.1261010","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1261010","url":null,"abstract":"We propose a new iterative approach that models the wirelength minimization problem as a minimum (potential) energy problem. The cell energy is the sum of the net energy (analogous to the spring elastic energy) and the overlap potential energy (analogous to the gravitational potential energy). Energy-based model is shown to be superior to the force-directed model.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122972697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A tunable g/sub m/-C filter with low variation across process, voltage and temperature","authors":"Q. Khan, S. Wadhwa, K. Misri","doi":"10.1109/ICVD.2004.1260975","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1260975","url":null,"abstract":"A tunable g/sub m/-C filter with cutoff frequency insensitive to Process, Voltage and Temperature is proposed. An external clock frequency is used to generate a current using a switched capacitor circuit. The proposed filter is ideally suited for applications where a tight control on cutoff frequency is desired across different operating conditions of the chip. The circuit was designed in 3.3 V BiCMOS technology and simulations were carried out using SPICE. The simulation results show that the total variation in the cutoff frequency is 1% as compared to the 27% variation in conventional g/sub m/-C filter over the temperature range of -40 to 120 degC. The variation across process corners is 2.4% and is almost independent of the capacitor variation due to process and temperature.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116826680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comparative study of low voltage OTA designs","authors":"D. Majumdar","doi":"10.1109/ICVD.2004.1260901","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1260901","url":null,"abstract":"The increased demand for Low Power/Low Voltage (LP/LV) circuits while maintaining high bandwidth and dynamic range, has led to widespread use of current-mode techniques in the design of analog circuits. Current trends in continual scaling down of transistor gate lengths and reduction in supply voltage have further added to the design challenges. This paper deals with the design of building blocks for current-mode circuit design, namely, Operational Transconductance Amplifier (OTA). Designs of three OTAs have been discussed. These OTAs operate at supply voltages about 3.3 V. Simulations have been carried out in Cadence (with Hspice) for Taiwan Semiconductor Manufacturing Corporation's (TSMC's) 0.35 /spl mu/m CMOS process. The main aim of this paper is to present and compare new OTA designs, which have potential for use in LV applications. One of the proposed OTAs has further been fabricated and tested for real-time application. The application addressed is that of designing spectral shaping filters for use in Second Generation High-bit-rate Digital Subscriber Line Technology (HDSL-2). The relative performance of all the three OTAs has also been presented.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129730169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Algorithmic macromodelling methods for mixed-signal systems","authors":"J. Roychowdhury","doi":"10.1109/ICVD.2004.1260916","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1260916","url":null,"abstract":"Electronic systems today, especially those for communications and sensing, are typically composed of a complex mix of digital and mixed-signal circuit blocks. Verifying such systems prior to fabrication is challenging due to their size and complexity. Automated model generation is becoming an increasingly important component of methodologies for effective system verification. In this paper, we review algorithmically-based model generation methods for linear and nonlinear systems. We comment on the development of such macromodelling methods over the last decade, clarify their domains of application and evaluate their strengths and current limitations.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128740709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The influence of process variations on the Halo MOSFETs and its implications on the analog circuit performance","authors":"K. Narasimhulu, S. Narendra, V. Rao","doi":"10.1109/ICVD.2004.1260976","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1260976","url":null,"abstract":"Lateral Asymmetric Channel (LAC) and Double Halo (DH) MOSFETs have been reported to exhibit excellent properties for mixed signal CMOS applications. In this work, the effect of process variations such as gate oxide thickness, implantation parameters, and channel length are systematically investigated on the device and analog circuit performance for all these technologies. The performance parameters of LAC and DH differential amplifiers and current mirror circuits are evaluated, using mixed-mode simulations, as a function of process induced mismatch. Our simulation results on differential amplifiers and current mirrors show that, an identical V, mismatch in CON, DH, and LAC devices results in a lower variation in the circuit parameters for LAC technologies. It is found that, for a specified circuit parameter variation, almost a 25% higher V, mismatch is tolerable with LAC technologies as compared to the CON technologies.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128738892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On-chip networks: a scalable, communication-centric embedded system design paradigm","authors":"J. Henkel, W. Wolf, S. Chakradhar","doi":"10.1109/ICVD.2004.1261037","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1261037","url":null,"abstract":"As chip complexity grows, design productivity boost is expected from reuse of large parts and blocks of previous designs with the design effort largely invested into the new parts. More and more processor cores and large, reusable components are being integrated on a single silicon die but reuse of the communication infrastructure has been difficult. Buses and point to point connections, that have been the main means to connect components on a chip today, will not result in a scalable platform architecture for the billion transistor chip era. Buses can cost efficiently connect a few tens of components. Point to point connections between communication partners is practical for even fewer components. As more and more components are integrated on a single silicon die, performance bottlenecks of long, global wires preclude reuse of buses. Therefore, scalable on-chip communication infrastructure is playing an increasingly dominant role in system-on-chip designs. With the super-abundance of cheap, function-specific IP cores, design effort will focus on the weakest link: efficient on-chip communication. Future on-chip communication infrastructure will overcome the limits of bus-based systems by providing higher bandwidth, higher flexibility and by solving the clock skew problem on large chips. It may, however, present new problems: higher power consumption of the communication infrastructure and harder-to-predict performance patterns. Solutions to these problems may result in a complete overhaul of SOC design methodologies into a communication-centric design style. The envisioning of upcoming problems and possible benefits has led to intensified research in the field of what is called NoCs: Networks on Chips. The term NoCs is used in a broad meaning, encompassing the hardware communication infrastructure, the middleware and operating system communication services, and a design methodology and tools to map applications onto a network on chip. This paper discusses trends in system-on-chip designs, critiques problems and opportunities of the NoC paradigm, summarizes research activities, and outlines several directions for future research.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121531755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Estimating pre-placement FPGA interconnection requirements","authors":"P. Kannan, D. Bhatia","doi":"10.1109/ICVD.2004.1261040","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1261040","url":null,"abstract":"With increasing device and design sizes, Interconnect Planning is fast becoming an important design issue for large FPGA based designs. The fundamental requirement for interconnect planning is the ability to estimate the routing requirements of a given design at all stages of physical design. A number of interconnect estimation methods have been proposed, but very few operate prior to placement. Pre-placement estimation is very useful for detailed design space exploration during logic synthesis and earlier stages of design. We propose a new local neighborhood analysis based method to estimate the wirelengths of every net in a given netlist, prior to placement. We assume an optimal placement with respect to total wirelength and estimate the bounding-box sizes of all the nets. We then use the bounding-box estimates to compute the post-routing peak channel width of the device. Our method efficiently handles pad constrained designs. We compare our net bounding-box and peak channel width estimates with the post-placement and post-routing results obtained using VPR, a commonly used FPGA tool suite.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125755284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Assertion based verification using HDVL","authors":"Kausik Datta, P. Das","doi":"10.1109/ICVD.2004.1260943","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1260943","url":null,"abstract":"Over the past several years verification of large designs are becoming more and more complex-both in terms of the maintaining the code size and in keeping parity between the specification written in English; design written in HDL (typically Verilog/VHDL) and the verification models-written in HDL or some proprietary verification language. To alleviate this problem, Accellera has come up with the proposal for standardizing an HDVL-a single language that caters to all the needs for Design (as an HDL) as well as Verification (as an HVL-Hardware Verification Language). System Verilog standard where the user can model and verify the correctness of the designs using a unified language whose syntax and semantics is already proven and tested in the industry is being projected as a candidate HDVL. SystemVerilog is a set of major enhancements to the Verilog 2001 standard and these enhancements are taken from existing industry standard languages and paradigms including Superlog, PSL-Sugar, OVA and OVL. In this paper we present an overview of the Assertion based Verification methodology in general and explain, with suitable examples, how can one benefit from using an HDVL for the combined purpose of design as well as verification. It attempts to set the right expectations for an engineer from an HDVL and also illustrates the power of the new paradigm.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130033623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Floorplan classification algorithms","authors":"Kun Gao, D. Mehta","doi":"10.1109/ICVD.2004.1261057","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1261057","url":null,"abstract":"We present optimal linear time algorithms that determine whether a given general floorplan represented by a q-sequence or twin binary trees is slicing or hierarchical. Experimental results on several benchmarks are presented.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134283896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design challenges in sub-100 nm high performance microprocessors","authors":"S. Narendra, V. Erraguntla, J. Tschanz, N. Borkar","doi":"10.1109/ICVD.2004.1260894","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1260894","url":null,"abstract":"This article deals with design challenges for high performance microprocessors. Device challenges including gate leakage, junction tunneling, junction depth scaling, parasitic series resistance, and short channel effects. Microprocessor frequencies are increasing every generation from additional architectural and circuit complexity, which demands higher level of integration and die size increase. To address these scaling challenges, devices, circuits and design methodologies need to evolve. Scaling gate oxide thickness is important for controlling short channel effects.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128956923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}