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Cosynthesis on multiprocessor architectures with high availability 高可用性多处理器体系结构上的协同合成
17th International Conference on VLSI Design. Proceedings. Pub Date : 2004-01-05 DOI: 10.1109/ICVD.2004.1261050
S. Chakraverty
{"title":"Cosynthesis on multiprocessor architectures with high availability","authors":"S. Chakraverty","doi":"10.1109/ICVD.2004.1261050","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1261050","url":null,"abstract":"The co-synthesis of hardware-software systems for distributed and/or embedded applications has been studied extensively in the recent past, in combination with various qualitative objectives. However, the issues related to design exploration for gracefully degrading systems with the specific objective of achieving the desired levels of availability need to be addressed systematically. In this paper, we propose a cosynthesis mechanism for generating gracefully degrading multiprocessor architectures which fulfill the dual objectives of achieving real-time performance as well as ensuring high levels of system availability as defined by the user's availability expectations under different states of functionality. A rule-based model for incorporating the user's availability requirements and evaluating the system availability is coupled with a stochastic scheduling technique and a genetic algorithm (GA) to optimize the resource selections, task allocations and task schedules. Results show that it is possible to obtain a range of near-optimal solutions, offering tradeoffs between performance and availability benefits at different costs.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132945999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Random access scan: a solution to test power, test data volume and test time 随机存取扫描:解决了测试功率、测试数据量和测试时间
17th International Conference on VLSI Design. Proceedings. Pub Date : 2004-01-05 DOI: 10.1109/ICVD.2004.1261042
D. Baik, K. Saluja, S. Kajihara
{"title":"Random access scan: a solution to test power, test data volume and test time","authors":"D. Baik, K. Saluja, S. Kajihara","doi":"10.1109/ICVD.2004.1261042","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1261042","url":null,"abstract":"Adherence to serial scan is preventing the researchers from investigating alternative design for test techniques that may offer larger test benefit at the cost of some what higher overhead. In this paper, we investigate the use of random access scan for simultaneous reduction of test power, test data volume and test application time. We provide an asymmetric traveling salesman formulation of these problems to minimize random access scans and the test data. Application of our method results into nearly 3/spl times/ speedup in test application time, 60% reduction in test data volume and over 99% reduction in power consumption for benchmark circuits.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133368245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 58
Neural network model for testing stuck-at and delay faults in digital circuit 数字电路卡滞和延迟故障检测的神经网络模型
17th International Conference on VLSI Design. Proceedings. Pub Date : 2004-01-05 DOI: 10.1109/ICVD.2004.1260970
P. Zhongliang
{"title":"Neural network model for testing stuck-at and delay faults in digital circuit","authors":"P. Zhongliang","doi":"10.1109/ICVD.2004.1260970","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1260970","url":null,"abstract":"The automatic test pattern generation techniques using artificial neural networks are studied. First, an optimal neural network model of digital circuits is investigated. The network model can represent a logic circuit by the minimal number of neurons. It is shown that there exist optimal neural networks for arbitrary logic circuits. We can get the network parameters by solving a system of linear equations. Second, a new energy model for delay faults testing of digital circuits is presented, which is based on the optimal neural network models. Third, it is shown that the test generation approach using the optimal neural network model can reduce the search space, and has better computation efficiency if compared with the circuit test methods using Hopfield binary neural network.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133682252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Embedded hardware face detection 嵌入式硬件人脸检测
17th International Conference on VLSI Design. Proceedings. Pub Date : 2004-01-05 DOI: 10.1109/ICVD.2004.1260915
T. Theocharides, G. Link, N. Vijaykrishnan, M. J. Irwin, W. Wolf
{"title":"Embedded hardware face detection","authors":"T. Theocharides, G. Link, N. Vijaykrishnan, M. J. Irwin, W. Wolf","doi":"10.1109/ICVD.2004.1260915","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1260915","url":null,"abstract":"Face detection is the first step towards face recognition and is a vital task in surveillance and security applications. Current software implementations of face detection algorithms lack the computational ability to support detection in real time video streams. Consequently, this work focuses on the design of special-purpose hardware for performing rotation invariant face detection. The synthesized design using 160 nm technology is found to operate at 409.5 kHz providing a throughput of 424 frames per second and consumes 7 Watts of power. The synthesized design provided 75% accuracy in detecting faces from a set of 55 images that is competitive with existing software implementations that provide around 80-85% accuracy.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132150430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 99
High-speed optoelectronics receivers in SiGe SiGe中的高速光电接收器
17th International Conference on VLSI Design. Proceedings. Pub Date : 2004-01-05 DOI: 10.1109/ICVD.2004.1261054
A. Gupta, S. Levitan, L. Selavo, D. Chiarulli
{"title":"High-speed optoelectronics receivers in SiGe","authors":"A. Gupta, S. Levitan, L. Selavo, D. Chiarulli","doi":"10.1109/ICVD.2004.1261054","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1261054","url":null,"abstract":"This paper focuses on the investigation of integrated CMOS and Silicon/Germanium (SiGe) devices for highspeed optical receiver circuits. In this paper, we present several competitive designs of front-end transimpedance amplifiers (TIA) for optical receiver applications using the IBM 5HP (0.5 micron) SiGe technology. This technology exhibits f/sub T/ and f/sub MAX/ of 47 GHz and 65 GHz respectively. Spectre simulations in the Cadence Affirma analog design environment are conducted for both the TIA's and a complete receiver circuit consisting of a TIA, a cascaded multi-stage differential amplifier and a multi-stage inverting amplifier at the single supply voltage of 3.3 V. We also discuss the practicality of using SiGe based photodetectors for 1.3-1.5 /spl mu/m wavelength light and the use of Neolinear's NeoCircuit/NeoCell mixed signal design tools for optimization of the analog circuits.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115623217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
NoCGEN:a template based reuse methodology for Networks On Chip architecture nogen:基于模板的芯片网络架构重用方法
17th International Conference on VLSI Design. Proceedings. Pub Date : 2004-01-05 DOI: 10.1109/ICVD.2004.1261011
J. Chan, S. Parameswaran
{"title":"NoCGEN:a template based reuse methodology for Networks On Chip architecture","authors":"J. Chan, S. Parameswaran","doi":"10.1109/ICVD.2004.1261011","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1261011","url":null,"abstract":"In this paper, we describe NoCGEN, a Network On Chip (NoC) generator, which is used to create a simulatable and synthesizable NoC description. NoCGEN uses a set of modularised router components that can be used to form different routers with a varying number of ports, routing algorithms, data widths and buffer depths. A graph description representing the interconnection between these routers is used to generate a top-level VHDL description. A wormhole output-queued 2-D mesh router was created to verify the capability of NoCGEN. Various parameterized designs were synthesized to provide estimated gate counts of 129 K to 695 K for a number of topologies varying from a 2/spl times/2 mesh to a 4/spl times/4 mesh, with constant data bus size width of 32. The NoC was simulated with random traffic using a mixed SystemC/VHDL environment to ensure correctness of operation and to obtain performance and average latency. The results show an accepted load of 53% to 55.6% with an increase in buffer depth from 8 to 32 flits for the 4/spl times/4 mesh router.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124493215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 88
VLSI implementation of visible watermarking for secure digital still camera design VLSI实现可见水印的安全数码相机设计
17th International Conference on VLSI Design. Proceedings. Pub Date : 2004-01-05 DOI: 10.1109/ICVD.2004.1261070
S. Mohanty, N. Ranganathan, R. Namballa
{"title":"VLSI implementation of visible watermarking for secure digital still camera design","authors":"S. Mohanty, N. Ranganathan, R. Namballa","doi":"10.1109/ICVD.2004.1261070","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1261070","url":null,"abstract":"Watermarking is the process that embeds data called a watermark into a multimedia object for its copyright protection. The digital watermarks can be visible to a viewer on careful inspection or completely invisible and cannot be easily recovered without an appropriate decoding mechanism. Digital image watermarking is a computationally intensive task and can be speeded up significantly by implementing in hardware. In this work, we describe a new VLSI architecture for implementing two different visible watermarking schemes for images. The proposed hardware can insert on-the-fly either one or both watermarks into an image depending on the application requirement. The proposed circuit can be integrated into any existing digital still camera framework. First, separate architectures are derived for the two watermarking schemes and then integrated into a unified architecture. A prototype CMOS VLSI chip was designed and verified implementing the proposed architecture and reported in this paper. To our knowledge, this is the first VLSI architecture for implementing visible watermarking schemes.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129041337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
Efficient algorithms for identifying the minimum leakage states in CMOS combinational logic CMOS组合逻辑中最小泄漏状态识别的有效算法
17th International Conference on VLSI Design. Proceedings. Pub Date : 2004-01-05 DOI: 10.1109/ICVD.2004.1260931
K. Chopra, S. Vrudhula, Sarvesh Bhardwaj
{"title":"Efficient algorithms for identifying the minimum leakage states in CMOS combinational logic","authors":"K. Chopra, S. Vrudhula, Sarvesh Bhardwaj","doi":"10.1109/ICVD.2004.1260931","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1260931","url":null,"abstract":"Power dissipation in CMOS circuits during inactive periods (static power) has become a significant part of the total power dissipation. This is particularly problematic for portable, battery powered systems, which are often in standby mode for long periods. It is well known that the major component of static power dissipation is due to subthreshold conduction. For individual gates, this leakage can vary by an order of magnitude over the gate's input states. Consequently, one way to minimize the leakage is to drive the inputs of the circuit to a state at which the leakage is minimum. In this paper, we present a new approach to identify all minimum leakage states. The method performs implicit enumeration based on integer valued decision diagrams. Since the search space for minimum leakage vector is exponential in the number of primary inputs, the enumeration is done with respect to the minimum balanced cut of the digraph representation of the circuit. The algorithm was successfully tested on the ISCAS85 and MCNC91 benchmark circuits.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130930105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A narrow pulse-suppressing filter for input buffer 用于输入缓冲器的窄脉冲抑制滤波器
17th International Conference on VLSI Design. Proceedings. Pub Date : 2004-01-05 DOI: 10.1109/ICVD.2004.1261007
P. Mandal
{"title":"A narrow pulse-suppressing filter for input buffer","authors":"P. Mandal","doi":"10.1109/ICVD.2004.1261007","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1261007","url":null,"abstract":"A narrow pulse-suppressing filter allows a wide pulse and blocks a narrow pulse. While existing pulse suppressing filters can block an isolated narrow pulse, they fail to stop a series of narrow pulses. Here we propose a different filter topology, which can suppress even an infinite series of narrow pulses. This is achieved by appropriately initializing the filter capacitor for every input transition edge, independent of whether the edge is successfully propagated to the output or not. Functionality of the proposed circuit is analyzed and demonstrated with Spice simulation.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127961641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Bridging the gap between asynchronous design and designers 弥合异步设计和设计师之间的差距
17th International Conference on VLSI Design. Proceedings. Pub Date : 2004-01-05 DOI: 10.1109/ICVD.2004.1260895
P. Beerel, J. Cortadella, A. Kondratyev
{"title":"Bridging the gap between asynchronous design and designers","authors":"P. Beerel, J. Cortadella, A. Kondratyev","doi":"10.1109/ICVD.2004.1260895","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1260895","url":null,"abstract":"This paper deals with the basic concepts of asynchronous circuits, state-of-the-art tools and methodologies for design of asynchronous circuits. This paper covers the aspects such as specification, architectural design and controller synthesis tools of asynchronous circuits. The design methodology of control circuits based on specifications with signal transition graphs is presented. This paper also deals with the design of complex circuits with different clock domains and desynchronisation of synchronous circuits.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131340675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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