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A 2.5 GHz CMOS fully-integrated /spl Delta//spl Sigma/-controlled fractional-N frequency synthesizer 2.5 GHz CMOS全集成/spl Delta//spl Sigma/控制分数n频率合成器
17th International Conference on VLSI Design. Proceedings. Pub Date : 2004-08-24 DOI: 10.1109/ICVD.2004.1260919
R. Dehghani
{"title":"A 2.5 GHz CMOS fully-integrated /spl Delta//spl Sigma/-controlled fractional-N frequency synthesizer","authors":"R. Dehghani","doi":"10.1109/ICVD.2004.1260919","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1260919","url":null,"abstract":"The design of a fully-integrated /spl Delta//spl Sigma/-controlled fractional-N frequency synthesizer is described. Using a dual modulus 64/72 prescaler based on injection locking technique and a novel third order digital /spl Delta//spl Sigma/ modulator, we achieved an extremely low power synthesizer in 2.5 GHz band. Total power dissipation of the frequency synthesizer is less than 6 mW at a 1.5 V supply. The loop bandwidth is optimized to achieve a -123 dBc/Hz phase noise at 3 MHz offset frequency. The locking time of the loop is less than 30 /spl mu/s.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115778923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A current sensor for on-chip, non-intrusive testing of RF systems 一种用于芯片上、非侵入式射频系统测试的电流传感器
17th International Conference on VLSI Design. Proceedings. Pub Date : 2004-01-05 DOI: 10.1109/ICVD.2004.1261064
Antonija Soldo, A. Gopalan, P. R. Mukund, M. Margala
{"title":"A current sensor for on-chip, non-intrusive testing of RF systems","authors":"Antonija Soldo, A. Gopalan, P. R. Mukund, M. Margala","doi":"10.1109/ICVD.2004.1261064","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1261064","url":null,"abstract":"This paper discusses design of a current sensor suitable for on-chip testing of RF circuits. The proposed sensor detects supply current (Idd) variations, with minimal impact on the circuit performance. Bandwidth of the circuit is 3.4 GHz, with a constant gain of 31.7 dB. The sensor has been implemented in IBM-6RF, 0.25 /spl mu/ CMOS technology, with 2.5 V power supply and it offers the low real estate overhead and high dynamic range required for this application.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"292 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115429964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Interconnect modeling for copper/low-k technologies 铜/低钾技术的互连建模
17th International Conference on VLSI Design. Proceedings. Pub Date : 2004-01-05 DOI: 10.1109/ICVD.2004.1260959
N. Nagaraj, T. Bonifield, Abha Singh, Roger Griesmer, P. Balsara
{"title":"Interconnect modeling for copper/low-k technologies","authors":"N. Nagaraj, T. Bonifield, Abha Singh, Roger Griesmer, P. Balsara","doi":"10.1109/ICVD.2004.1260959","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1260959","url":null,"abstract":"Interconnect parasitics are significant and complex components of circuit performance, signal integrity and reliability in IC design. Copper/low-k process effects are becoming increasingly important to accurately model interconnect parasitics. In this tutorial, four key aspects of copper/low-k interconnect process are discussed: Non-linear resistance, Selective Process Bias (SPB), dummy (fill) metal and process variations. Even if the interconnect process profile is accurately represented, approximations in parasitic extraction could cause large errors. Techniques used in parasitic extraction to model the copper/low-k effects are discussed in detail. Techniques to measure resistance and capacitance in silicon and correlating them to parasitic extraction tools are presented to demonstrate systematic validation interconnect parasitics.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124274377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Bridge over troubled wrappers:automated interface synthesis 跨越麻烦包装器的桥梁:自动界面合成
17th International Conference on VLSI Design. Proceedings. Pub Date : 2004-01-05 DOI: 10.1109/ICVD.2004.1260923
V. D'Silva, S. Ramesh, A. Sowmya
{"title":"Bridge over troubled wrappers:automated interface synthesis","authors":"V. D'Silva, S. Ramesh, A. Sowmya","doi":"10.1109/ICVD.2004.1260923","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1260923","url":null,"abstract":"System-on-Chip (SoC) design methodologies rely heavily on reuse of intellectual property (IP) blocks. IP reuse is a labour intensive and time consuming process as IP blocks often have different communication interfaces. We present an algorithm which automates the generation of provably correct HDL descriptions of interfaces between mismatched IP communication protocols. We significantly improve and extend existing work by providing a solution which addresses data mismatches, pipelining and differences in clock speeds. These ideas have been implemented and the tool has been used to synthesise wrappers and bridges for many SoC protocols.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117153996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
Formal verification of C language based VLSI designs 基于C语言的VLSI设计的形式化验证
17th International Conference on VLSI Design. Proceedings. Pub Date : 2004-01-05 DOI: 10.1109/ICVD.2004.1260908
M. Fujita
{"title":"Formal verification of C language based VLSI designs","authors":"M. Fujita","doi":"10.1109/ICVD.2004.1260908","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1260908","url":null,"abstract":"This paper discusses about formal verification techniques targeting C based VLSI design descriptions. Recently there are lots of attentions into the use of C programming language (or its extensions) for describing hardware as well as software with an intention to support hardware-software co-design processes with a single language. Here we first discuss about such design methodologies by which system level descriptions for hardware-software combined systems can be uniformly and smoothly refined into implementation in RTL for hardware and assembly languages for software. Starting from regular C programming language descriptions, the design methodologies repeat a number of small refinement steps and gradually adding more and more details into the target designs. We also discuss about formal verification of system level descriptions in those design methodologies from the viewpoint of formal verification. Since such descriptions have essentially concurrency and C must be extended to be able to represent such concurrency, an effective and efficient formal verification of synchronization of concurrent processes is one of the most important issues in system level designs. We present model checking and equivalence checking methods targeting the design methodology that can check correctness of design descriptions with preliminary experimental results. The proposed formal verification methods will support the design methodologies and are very efficient by utilizing the fact that the design methodologies consist of lots of small refinement steps.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126053834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
High speed integrated A to D converters 高速集成A - D转换器
17th International Conference on VLSI Design. Proceedings. Pub Date : 2004-01-05 DOI: 10.1109/ICVD.2004.1260898
P. Jespers
{"title":"High speed integrated A to D converters","authors":"P. Jespers","doi":"10.1109/ICVD.2004.1260898","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1260898","url":null,"abstract":"This article deals about high speed integrated A to D converters. Flash converters achieve A to D conversion in a single clock cycle. They are fast devices by essence but area and power consumption increase exponentially with numbers of bits. Nine to ten-bit converters require large transistor sizes in order to cope with narrow offset tolerances of the comparators. Five to six bit resolution full-flash converters are more customary. Multistep converters take advantage of low-resolution flash devices. Full-flash converters is known as folding converters. The number of comparators is smaller than with full-flash devices to interpolation techniques. A 10-bit CMOS converter with a sample rate of 50 MS/s and 240mW power consumption has been reported.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126148766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Synthesis-driven exploration of pipelined embedded processors 流水线嵌入式处理器的综合驱动探索
17th International Conference on VLSI Design. Proceedings. Pub Date : 2004-01-05 DOI: 10.1109/ICVD.2004.1261049
P. Mishra, A. Kejariwal, N. Dutt
{"title":"Synthesis-driven exploration of pipelined embedded processors","authors":"P. Mishra, A. Kejariwal, N. Dutt","doi":"10.1109/ICVD.2004.1261049","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1261049","url":null,"abstract":"Recent advances on language based software toolkit generation enables performance driven exploration of embedded systems by exploiting the application behavior. There is a need for an automatic generation of hardware to determine the required silicon area, clock frequency, and power consumption of the candidate architectures. In this paper, we present a language based exploration framework that automatically generates synthesizable RTL models for pipelined processors. Our framework allows varied micro-architectural modifications, such as, addition of pipeline stages, pipeline paths, opcodes and new functional units. The generated RTL is synthesized to determine the area, power, and clock frequency of the modified architectures. Our exploration results demonstrate the power of reuse in composing heterogeneous architectures using functional abstraction primitives allowing for a reduction in the time for specification and exploration by at least an order of magnitude.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114955702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
Improved approach for noise propagation to identify functional noise violations 改进的噪声传播方法以识别功能性噪声冲突
17th International Conference on VLSI Design. Proceedings. Pub Date : 2004-01-05 DOI: 10.1109/ICVD.2004.1261008
Sachin Shrivastava, Dhanoop Varghese, V. Narang, N. Arvind
{"title":"Improved approach for noise propagation to identify functional noise violations","authors":"Sachin Shrivastava, Dhanoop Varghese, V. Narang, N. Arvind","doi":"10.1109/ICVD.2004.1261008","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1261008","url":null,"abstract":"This paper targets at reducing the crosstalk noise closure time by filtering the set of false violations. We propose two approaches to reduce the pessimism in the crosstalk noise analysis. The first approach uses the arrival time windows for glitch propagation. The second approach uses the critical window of the sequential cell pins to identify the violations. We have presented some results that show the reduction in number of violation with new approach.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115057721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design of RF tuner for cable modem applications 电缆调制解调器射频调谐器的设计
17th International Conference on VLSI Design. Proceedings. Pub Date : 2004-01-05 DOI: 10.1109/ICVD.2004.1260955
V. Babu, Sumantra Seth, A. Chandorkar
{"title":"Design of RF tuner for cable modem applications","authors":"V. Babu, Sumantra Seth, A. Chandorkar","doi":"10.1109/ICVD.2004.1260955","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1260955","url":null,"abstract":"An integrated RF tuner, operating in 40 MHz- 900 MHz bandwidth for cable modem is presented using TSMC 0.35 /spl mu/m (four metal, double poly) process. RF tuners always have external components which increases board space and cost. The complete monolithic RF tuner will be a cost, area and power efficient solution for DOCSIS standard high speed (10 Mbps-30 Mbps) cable modems. The designed RF tuner has an end to end gain of 0 dB, and adjacent channel rejection of -34 dB without any external SAW filters. The total area is 3m.m./spl times/3m.m. with a power consumption of 680 mW with a 3.3V supply.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115100147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Physical design trends and layout-based fault modeling 物理设计趋势和基于布局的故障建模
17th International Conference on VLSI Design. Proceedings. Pub Date : 2004-01-05 DOI: 10.1109/ICVD.2004.1260891
S. Sur-Kolay, P. Dasgupta, B. Bhattacharya, S. Zachariah
{"title":"Physical design trends and layout-based fault modeling","authors":"S. Sur-Kolay, P. Dasgupta, B. Bhattacharya, S. Zachariah","doi":"10.1109/ICVD.2004.1260891","DOIUrl":"https://doi.org/10.1109/ICVD.2004.1260891","url":null,"abstract":"This paper presents the concerns and techniques that are significant to both the circuit designers and developers of CAD tools for physical design and layout-based fault modeling and extraction. Current technology trends in VLSI with their impacts on the design flow in general and physical design in particular are introduced. The challenging issues in partitioning, floorplanning and placement, and routing are presented. Recent topics in deep sub-micron (DSM) regime are presented. Finally device scaling has led to blurring of the boundary between design and test and eroded the predictability of test quality based on classical stuck-at fault coverage. New fault models at the core of test generation to overcome the test quality crisis are described.","PeriodicalId":262556,"journal":{"name":"17th International Conference on VLSI Design. Proceedings.","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116432425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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