2015 International Conference on Field Programmable Technology (FPT)最新文献_第3页

Bringing programmability to the data plane: Packet processing with a NoC-enhanced FPGA 将可编程性引入数据平面:使用noc增强的FPGA进行分组处理

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393125

Andrew Bitar, M. Abdelfattah, Vaughn Betz

引用次数: 18

FPGA acceleration of reference-based compression for genomic data 基于参考的基因组数据压缩FPGA加速

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393126

James Arram, Moritz Pflanzer, Thomas Kaplan, W. Luk

引用次数: 12

HETRIS: Adaptive floorplanning for heterogeneous FPGAs HETRIS:异构fpga的自适应布局

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393136

Kevin E. Murray, Vaughn Betz

引用次数: 5

Lower precision for higher accuracy: Precision and resolution exploration for shallow water equations 低精度求高精度:浅水方程的精度和分辨率探索

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393152

James Stanley Targett, Xinyu Niu, F. P. Russell, W. Luk, S. Jeffress, P. Düben

引用次数: 6

OpenCL library of stream memory components targeting FPGAs 针对fpga的流存储器组件的OpenCL库

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393134

Jasmina Vasiljevic, Ralph Wittig, P. Schumacher, Jeff Fifield, F. Martinez-Vallina, Henry Styles, P. Chow

{"title":"OpenCL library of stream memory components targeting FPGAs","authors":"Jasmina Vasiljevic, Ralph Wittig, P. Schumacher, Jeff Fifield, F. Martinez-Vallina, Henry Styles, P. Chow","doi":"10.1109/FPT.2015.7393134","DOIUrl":"https://doi.org/10.1109/FPT.2015.7393134","url":null,"abstract":"In recent years, high-level languages and compilers, such as OpenCL have improved both productivity and FPGA adoption on a wider scale. One of the challenges in the design of high-performance stream FPGA applications is iterative manual optimization of the numerous application buffers (e.g., arrays, FIFOs and scratch-pads). First, to achieve the desired throughput, the programmer faces the burden of analyzing the memory accesses of each application buffer, and based on observed data locality determines the optimal on-chip buffering, and off-chip read/write data access strategy. Second, to minimize throughput bottlenecks, the programmer has to carefully partition the limited on-chip memory resources among many application buffers. In this work we present an FPGA OpenCL library of pre-optimized stream memory components (SMCs). The library contains three types of SMCs, which implement frequently applied data transformations: 1) stencil, 2) transpose and 3) tiling. The library generates SMCs that are optimized both for the specific data transformation they perform as well as the user specified data set size. Further, to ease the partitioning of on-chip memory resources among many application memories, the library automatically maps application buffers to on-chip and off-chip memory resources. This is achieved by enabling the programmer to specify an on-chip memory budget for each component. In terms of on-chip memory, the SMCs perform data buffering to exploit data locality and maximize reuse. In terms of off-chip memory accesses, the SMCs optimize read/write memory operations by performing data coalescing, bursting and prefetching. We show that using the SMC library, the programmer can quickly generate scalable, pre-optimized stream application memory components, thus reaching throughput targets without time consuming manual memory optimization.","PeriodicalId":261246,"journal":{"name":"2015 International Conference on Field Programmable Technology (FPT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132000547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

FPGA implementation of a SIMD-based array processor with torus interconnect 基于simd的环面互连阵列处理器的FPGA实现

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393159

Yuki Murakami

引用次数: 3

Advanced Bayer demosaicing on FPGAs fpga上的高级拜耳反马赛克

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393154

D. Bailey, S. Randhawa, J. Li

引用次数: 6

An architecture-algorithm co-design of artificial intelligence for Trax player Trax播放器人工智能的架构-算法协同设计

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393120

Qing Lu, Chiu-Wing Sham, F. Lau

引用次数: 3

Improved carry chain mapping for the VTR flow 改进进位链映射的VTR流

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393133

A. Petkovska, Grace Zgheib, D. Novo, Muhsen Owaida, A. Mishchenko, P. Ienne

{"title":"Improved carry chain mapping for the VTR flow","authors":"A. Petkovska, Grace Zgheib, D. Novo, Muhsen Owaida, A. Mishchenko, P. Ienne","doi":"10.1109/FPT.2015.7393133","DOIUrl":"https://doi.org/10.1109/FPT.2015.7393133","url":null,"abstract":"Carry chains facilitate the implementation of adders and improve the performance of arithmetic circuits in FPGAs. The last version of the commonly used open-source Verilog-to-Routing (VTR) CAD flow now enables modelling carry chains in FPGA architectures. However, one of the shortcomings of the existing flow lies in its inability to identify arithmetic operations when described as gate-level circuits. Moreover, the VTR flow squanders most of the LUTs preceding the chain logic. This paper focuses on these two problems and proposes preprocessing the circuit before technology mapping to allow for a more efficient use of carry chains. The first proposed method maps logic on the carry chains for circuits expressed using a gate-level description. On average, it identifies about 30% more meaningful full adders than the existing tool flow operating on the RTL descriptions. Area is thus improved by up to 15% with an average of 6% for almost no delay penalty. Secondly, we increase the use of the LUTs preceding the chain logic by a factor 2 on average. This reduces delay (up to 9%) and area (up to 2%), compared to the existing VTR flow. The new approach is independent of the specific carry-chain architecture and can be generically adapted to any FPGA with built-in hardened adders.","PeriodicalId":261246,"journal":{"name":"2015 International Conference on Field Programmable Technology (FPT)","volume":"28 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123084427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Development of a Trax Artificial Intelligence algorithm using path and edge 一种基于路径和边缘的Trax人工智能算法的开发

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393118

Ryou Okuda, Tomohiro Tanaka, Keisuke Yamamoto, Takumu Yahagi, K. Tanigawa

引用次数: 4