2015 International Conference on Field Programmable Technology (FPT)最新文献_第2页

A self-aware data compression system on FPGA in Hadoop 基于FPGA的Hadoop自感知数据压缩系统

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393149

Yubin Li, Yuliang Sun, Guohao Dai, Yuzhi Wang, Jiacai Ni, Yu Wang, Guoliang Li, Huazhong Yang

引用次数: 5

Braiding: A scheme for resolving hazards in kernel adaptive filters 编织:核自适应滤波器中危险的一种解决方案

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393140

Stephen Tridgell, Duncan J. M. Moss, Nicholas J. Fraser, P. Leong

引用次数: 4

Comparison of thread signatures for error detection in hybrid multi-cores 混合多核错误检测的线程签名比较

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393153

S. Meisner, M. Platzner

引用次数: 1

Trax solver on Zynq with Deep Q-Network 基于Deep Q-Network的Zynq Trax求解器

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393122

N. Sugimoto, Takuji Mitsuishi, Takahiro Kaneda, Chiharu Tsuruta, Ryotaro Sakai, Hideki Shimura, H. Amano

引用次数: 5

QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlay QuickDough:一个使用软CGRA覆盖的快速FPGA环路加速器设计框架

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393130

Cheng Liu, Ho-Cheung Ng, Hayden Kwok-Hay So

{"title":"QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlay","authors":"Cheng Liu, Ho-Cheung Ng, Hayden Kwok-Hay So","doi":"10.1109/FPT.2015.7393130","DOIUrl":"https://doi.org/10.1109/FPT.2015.7393130","url":null,"abstract":"The use of FPGAs as compute accelerators has been demonstrated by numerous researchers as an effective solution to meet the performance requirement across many application domains. However, the design productivity of developing FPGA accelerators remains much lower compared to the use of a typical software development flow. Although the use of the high-level design tools may partly alleviate this shortcoming, the lengthy low-level FPGA implementation process including synthesis, placing and routing still dramatically limits the number of compile-debug-edit cycles per day and hinders the widespread adoption of FPGAs. To address this design productivity problem, we have developed a rapid FPGA loop accelerator generation framework called QuickDough. By utilizing a soft coarse-grained reconfigurable array (SCGRA) overlay built on top of off-the-shelf FPGAs, it compiles a high-level loop to the overlay through a rapid operation scheduling first and then generates the FPGA accelerator bitstream through a rapid integration of the scheduling result and a pre-built overlay bitstream. According to the experiments, QuickDough is able to produce accelerators in the order of seconds while achieving up to 9X performance speedup over the execution of the same software running on a hard ARM processor.","PeriodicalId":261246,"journal":{"name":"2015 International Conference on Field Programmable Technology (FPT)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125380751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 44

Leftmost longest regular expression matching in reconfigurable logic 可重构逻辑中最左边最长的正则表达式匹配

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393124

K. Atasu

引用次数: 1

Automatic FPGA system and interconnect construction with multicast and customizable topology 自动FPGA系统和具有多播和可定制拓扑的互连结构

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393132

A. Rodionov, Jonathan Rose

引用次数: 4

Smart camera for Trax playing robot Trax游戏机器人的智能摄像头

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393117

D. Bailey

引用次数: 0

FPGA based acceleration of FDAS module for Pulsar Search 基于FPGA的脉冲星搜索FDAS模块加速

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393158

Haomiao Wang, O. Sinnen

引用次数: 5

Custom-sized caches in application-specific memory hierarchies 在特定于应用程序的内存层次结构中自定义大小的缓存

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393141

F. Winterstein, Kermin Fleming, Hsin-Jung Yang, John Wickerson, G. Constantinides

{"title":"Custom-sized caches in application-specific memory hierarchies","authors":"F. Winterstein, Kermin Fleming, Hsin-Jung Yang, John Wickerson, G. Constantinides","doi":"10.1109/FPT.2015.7393141","DOIUrl":"https://doi.org/10.1109/FPT.2015.7393141","url":null,"abstract":"Developing FPGA implementations with an input specification in a high-level programming language such as C/C++ or OpenCL allows for a substantially shortened design cycle compared to a design entry at register transfer level. This work targets high-level synthesis (HLS) implementations that process large amounts of data and therefore require access to an off-chip memory. We leverage the customizability of the FPGA on-chip memory to automatically construct a multi-cache architecture in order to enhance the performance of the interface between parallel functional units of the HLS core and an external memory. Our focus is on automatic cache sizing. Firstly, our technique determines and uses up unused left-over block RAM resources for the construction of on-chip caches. Secondly, we devise a high-level cache performance estimation based on the memory access trace of the program. We use this memory trace to find a heterogeneous configuration of cache sizes, tailored to the application's memory access characteristic, that maximizes the performance of the multi-cache system subject to an on-chip memory resource constraint. We evaluate our technique with three benchmark implementations on an FPGA board and obtain a reduction in execution latency of up to 2× (1.5× on average) when compared to a one-size-fits-all cache sizing. We also quantify the impact of our automatically generated cache system on the overall energy consumption of the implementation.","PeriodicalId":261246,"journal":{"name":"2015 International Conference on Field Programmable Technology (FPT)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131493597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13