2015 International Conference on Field Programmable Technology (FPT)最新文献

An adaptive cross-layer fault recovery solution for reconfigurable SoCs 面向可重构soc的自适应跨层故障恢复方案

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393147

Jifang Jin, Jian Yan, Xuegong Zhou, Lingli Wang

引用次数: 0

A co-design approach for accelerated SQL query processing via FPGA-based data filtering 基于fpga的数据过滤加速SQL查询处理的协同设计方法

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393148

Andreas Becher, Daniel Ziener, K. Meyer-Wegener, J. Teich

{"title":"A co-design approach for accelerated SQL query processing via FPGA-based data filtering","authors":"Andreas Becher, Daniel Ziener, K. Meyer-Wegener, J. Teich","doi":"10.1109/FPT.2015.7393148","DOIUrl":"https://doi.org/10.1109/FPT.2015.7393148","url":null,"abstract":"In this paper, we present a novel co-designed architecture for high throughput database query processing. It consists of a highly configurable FPGA-based filter chain with arithmetic operation support and an alignment unit. This feeds the filtered data directly and in a cache-optimized way to embedded processors which are responsible for joining tables and post processing. High throughput interfaces and parallelism of FPGA implementations are thus combined in order to provide reduced and cache-aligned data for optimized processor access. As a key component, we introduce a new highly configurable bloom filter cascade to relieve a processor of time-consuming hash-value computation and to significantly reduce the data for hash joins. It is shown that this unique approach may reduce the amount of data to be processed by the processors in typical data-warehouse applications by several orders of magnitude. The proposed co-design has been implemented on the embedded low-energy system-on-chip (SoC) platform Xilinx Zynq. Performance results for standard benchmarks show an up to 10 x higher throughput compared to a full featured x86-based processor at only a fraction of energy consumption.","PeriodicalId":261246,"journal":{"name":"2015 International Conference on Field Programmable Technology (FPT)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127704181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 27

An FPGA-based real-time simultaneous localization and mapping system 基于fpga的实时同步定位与制图系统

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393150

Mengyuan Gu, Kaiyuan Guo, Wenqiang Wang, Yu Wang, Huazhong Yang

引用次数: 13

Using Round-Robin Tracepoints to debug multithreaded HLS circuits on FPGAs 使用循环跟踪点调试fpga上的多线程HLS电路

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393128

Jeffrey B. Goeders, S. Wilton

{"title":"Using Round-Robin Tracepoints to debug multithreaded HLS circuits on FPGAs","authors":"Jeffrey B. Goeders, S. Wilton","doi":"10.1109/FPT.2015.7393128","DOIUrl":"https://doi.org/10.1109/FPT.2015.7393128","url":null,"abstract":"High-level synthesis (HLS) for FPGA designs has gained significant traction in recent years. A key component in its adoption is allowing users to debug their hardware systems in the context of the original source code. This is becoming even more challenging as modern HLS tools enable the user to provide multithreaded source code for synthesis to hardware. Although recent work has begun to tackle source-level debugging of HLS circuits, none have addressed doing this in multithreaded circuits. In such systems it may be necessary to observe the behaviour of multiple threads for long run times in order to locate obscure or non-deterministic bugs and performance issues. In this paper we present a trace-based debugging architecture which records values from user-selected tracepoints into on-chip memories during circuit execution. The recorded values can be provided to the user as a cycle-accurate timeline of events to aid them in debugging multithreaded HLS circuits. We present a novel technique to allow multiple hardware threads to share trace buffers, effectively increasing the execution trace that can be recorded. This is accomplished by analyzing the control and data flow graph to determine the maximum rates at which each thread can encounter tracepoints, using this information to select which threads can share trace buffers, and automatically generating round-robin circuitry to arbitrate access to the buffers. Using this technique we are able to obtain an average of 4X improvement in trace length for an 8 thread system. This provides users with a longer timeline of execution and greater visibility into the execution of multithreaded HLS circuits.","PeriodicalId":261246,"journal":{"name":"2015 International Conference on Field Programmable Technology (FPT)","volume":"64 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124098162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

FPGA Trax Solver based on a neural network design 基于神经网络的FPGA Trax求解器设计

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393119

Takumi Fujimori, Tomoya Akabe, Yoshizumi Ito, Kouta Akagi, Shinya Furukawa, Hiroki Shinba, Aoi Tanibata, Minoru Watanabe

引用次数: 3

2D Discrete Fourier Transform with simultaneous edge artifact removal for real-time applications 二维离散傅里叶变换与同时边缘伪影去除实时应用

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393157

Faisal Mahmood, M. Toots, L. Ofverstedt, U. Skoglund

{"title":"2D Discrete Fourier Transform with simultaneous edge artifact removal for real-time applications","authors":"Faisal Mahmood, M. Toots, L. Ofverstedt, U. Skoglund","doi":"10.1109/FPT.2015.7393157","DOIUrl":"https://doi.org/10.1109/FPT.2015.7393157","url":null,"abstract":"Two-Dimensional (2D) Discrete Fourier Transform (DFT) is a basic and computationally intensive algorithm, with a vast variety of applications. 2D images are, in general, non-periodic, but are assumed to be periodic while calculating their DFTs. This leads to cross-shaped artifacts in the frequency domain due to spectral leakage. These artifacts can have critical consequences if the DFTs are being used for further processing. In this paper we present a novel FPGA-based design to calculate high-throughput 2D DFTs with simultaneous edge artifact removal. Standard approaches for removing these artifacts using apodization functions or mirroring, either involve removing critical frequencies or a surge in computation by increasing image size. We use a periodic-plus-smooth decomposition based artifact removal algorithm optimized for FPGA implementation, while still achieving real-time (≥23 frames per second) performance for a 512×512 size image stream. Our optimization approach leads to a significant decrease in external memory utilization thereby avoiding memory conflicts and simplifies the design. We have tested our design on a PXIe based Xilinx Kintex 7 FPGA system communicating with a host PC which gives us the advantage to further expand the design for industrial applications.","PeriodicalId":261246,"journal":{"name":"2015 International Conference on Field Programmable Technology (FPT)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131493140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Accelerated cell imaging and classification on FPGAs for quantitative-phase asymmetric-detection time-stretch optical microscopy 用于定量相位非对称检测时间拉伸光学显微镜的fpga加速细胞成像和分类

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393123

Junyi Xie, Xinyu Niu, Andy K. S. Lau, K. Tsia, Hayden Kwok-Hay So

{"title":"Accelerated cell imaging and classification on FPGAs for quantitative-phase asymmetric-detection time-stretch optical microscopy","authors":"Junyi Xie, Xinyu Niu, Andy K. S. Lau, K. Tsia, Hayden Kwok-Hay So","doi":"10.1109/FPT.2015.7393123","DOIUrl":"https://doi.org/10.1109/FPT.2015.7393123","url":null,"abstract":"With the fundamental trade-off between speed and sensitivity, existing quantitative phase imaging (QPI) systems for diagnostics and cell classification are often limited to batch processing only small amount of offline data. While quantitative asymmetric-detection time-stretch optical microscopy (Q-ATOM) offers a unique optical platform for ultrafast and high-sensitivity quantitative phase cellular imaging, performing the computationally demanding backend QPI phase retrieval and image classification in real-time remains a major technical challenge. In this paper, we propose an optimized architecture for QPI on FPGA and compare its performance against CPU and GPU implementations in terms of speed and power efficiency. Results show that our implementation on single FPGA card demonstrates a speedup of 9.4 times over an optimized C implementation running on a 6-core CPU, and 3.47 times over the GPU implementation. It is also 24.19 and 4.88 times more power-efficient than the CPU and GPU implementation respectively. Throughput increase linearly when four FPGA cards are used to further improve the performance. We also demonstrate an increased classification accuracy when phase images instead of single-angle ATOM images are used. Overall, one FPGA card is able to process and categorize 2497 cellular images per second, making it suitable for real-time single-cell analysis applications.","PeriodicalId":261246,"journal":{"name":"2015 International Conference on Field Programmable Technology (FPT)","volume":"209 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121273912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Using source-to-source compilation to instrument circuits for debug with High Level Synthesis 使用源对源编译仪器电路调试与高级合成

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393129

Joshua S. Monson, B. Hutchings

引用次数: 11

Resource and memory management techniques for the high-level synthesis of software threads into parallel FPGA hardware 用于将软件线程高级合成为并行FPGA硬件的资源和内存管理技术

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393142

Jongsok Choi, S. Brown, J. Anderson

{"title":"Resource and memory management techniques for the high-level synthesis of software threads into parallel FPGA hardware","authors":"Jongsok Choi, S. Brown, J. Anderson","doi":"10.1109/FPT.2015.7393142","DOIUrl":"https://doi.org/10.1109/FPT.2015.7393142","url":null,"abstract":"Recent work has proposed the high-level synthesis of parallel software programs (specified using Pthreads or OpenMP) into concurrently operating parallel hardware modules [6]. In this paper, we describe resource and memory management techniques for improving performance and area of hardware generated by such software thread synthesis. One direction investigated pertains to how modules in the HLS-generated parallel hardware should connect to one another: 1) with a nested topology, or 2) with a flat topology. In the nested topology, hardware modules are created in a hierarchical manner: modules are instantiated inside within modules that use them. Conversely, the flat topology instantiates all hardware modules at the same level of hierarchy. For the flat topology, we describe a system generator that automatically generates the required interconnect between all hardware modules, as well as flexibly shares or replicates functions, functional units, and memories. We also explore methods to reduce memory contention among hardware units that operate in parallel, by investigating three different memory architectures which use: 1) a global memory controller, 2) local memories, and 3) shared-local memories. Local and shared-local memories are dedicated RAM blocks for a single or a set of hardware modules, and help to increase memory bandwidth by allowing concurrent memory accesses. We also consider memory replication to localize memories in hardware modules, and convert small memories to registers to further improve performance and memory usage. Finally, we describe implementing locks and barriers in HLS hardware: synchronization constructs used in parallel programming. We show that with our resource and memory management techniques, we can improve the geomean performance, area, and area-delay product of parallel HLS-generated hardware up to 41.6%, 38.3%, and 63.3%, respectively, for a set of 15 benchmarks.","PeriodicalId":261246,"journal":{"name":"2015 International Conference on Field Programmable Technology (FPT)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122085887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Optimized high-level synthesis of SMT multi-threaded hardware accelerators SMT多线程硬件加速器的优化高级合成

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393145

Jens Huthmann, A. Koch

{"title":"Optimized high-level synthesis of SMT multi-threaded hardware accelerators","authors":"Jens Huthmann, A. Koch","doi":"10.1109/FPT.2015.7393145","DOIUrl":"https://doi.org/10.1109/FPT.2015.7393145","url":null,"abstract":"Recent high-level synthesis tools offer the capability to generate multi-threaded micro-architectures to hide memory access latencies. In many HLS flows, this is often achieved by just creating multiple processing element-instances (one for each thread). However, more advanced compilers can synthesize hardware in a spatial form of the barrel processor- or simultaneous multi-threading (SMT) approaches, where only state storage is replicated per thread, while the actual hardware operators in a single datapath are re-used between threads. The spatial nature of the micro-architecture applies not only to the hardware operators, but also to the thread scheduling facility, which itself is spatially distributed across the entire datapath in separate hardware stages. Since each of these thread scheduling stages, which also allow a re-ordering of threads, adds hardware overhead, it is worthwhile to examine how their number can be reduced while maintaining the performance of the entire datapath. We report on a number of thinning options and examine their impact on system performance. For kernels from the MachSuite HLS benchmark collection, we have achieved area savings of up to 50% LUTs and 50% registers, while maintaining full performance for the compiled hardware accelerators.","PeriodicalId":261246,"journal":{"name":"2015 International Conference on Field Programmable Technology (FPT)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126505366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5