2015 International Conference on Field Programmable Technology (FPT)最新文献_第4页

Hardware design of a fast, parallel Random Tree path planner 硬件设计一个快速、并行的随机树路径规划器

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393151

Size Xiao, A. Postula, N. Bergmann

{"title":"Hardware design of a fast, parallel Random Tree path planner","authors":"Size Xiao, A. Postula, N. Bergmann","doi":"10.1109/FPT.2015.7393151","DOIUrl":"https://doi.org/10.1109/FPT.2015.7393151","url":null,"abstract":"The Rapidly-Exploring Random Trees (RRT) method has been proved successful and efficient for solving path planning problems. Most recent work focuses on optimizing RRT itself and presents the results achieved from software. In this paper a dedicated hardware architecture for FPGA implementation of Rapidly-Exploring Random Tree (RRT) path planning is developed. The proposed architecture fully takes advantage of FPGAs' natural parallel computing ability. The near neighbour (NN) search speed is improved by splitting the whole search space into several sub-spaces; correspondingly the tree nodes are stored in separate block RAMs and each Block RAM owns its independent traversal query module to enhance the memory throughput. Furthermore, to speed up the space exploration, each single path planning unit consists of two cooperating RRT modules which grow trees from each end of the path. One complete path planner involves several path planning units which work in a parallel master-slave mode to increase the probability of obtaining available path. Implementation in a 2D environment shows good path planning performance of the hardware design, with a 30x speed improvement compared to a PC implementation.","PeriodicalId":261246,"journal":{"name":"2015 International Conference on Field Programmable Technology (FPT)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131081784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Minimizing DSP block usage through multi-pumping 通过多泵送最小化DSP块的使用

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393146

Bajaj Ronak, Suhaib A. Fahmy

引用次数: 7

FPGA implementation of low-power and high-PSNR DCT/IDCT architecture based on adaptive recoding CORDIC 基于CORDIC自适应编码的低功耗高psnr DCT/IDCT结构的FPGA实现

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393139

Jianfeng Zhang, P. Chow, Hengzhu Liu

引用次数: 7

Provably Correct Development of reconfigurable hardware designs via equational reasoning 通过方程推理开发可重构硬件设计

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393143

I. Graves, A. Procter, W. Harrison, G. Allwein

引用次数: 7

JIT trace-based verification for high-level synthesis 用于高级合成的基于JIT跟踪的验证

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393155

Liwei Yang, Magzhan Ikram, S. Gurumani, Suhaib A. Fahmy, Deming Chen, K. Rupnow

{"title":"JIT trace-based verification for high-level synthesis","authors":"Liwei Yang, Magzhan Ikram, S. Gurumani, Suhaib A. Fahmy, Deming Chen, K. Rupnow","doi":"10.1109/FPT.2015.7393155","DOIUrl":"https://doi.org/10.1109/FPT.2015.7393155","url":null,"abstract":"High level synthesis (HLS) tools are increasingly adopted for hardware design as the quality of tools consistently improves. Concerted development effort on HLS tools represents significant software development effort, and debugging and validation represents a significant portion of that effort. However, HLS tools are different from typical large-scale software systems; HLS tool output must be subsequently verified through functional verification of the generated RTL implementation. Debugging machine-generated functionally incorrect RTL is time-consuming and cumbersome requiring back-tracing through hundreds of signals and simulation cycles to determine the underlying error. This challenging process requires support framework in the HLS flow to enable fast and efficient pinpointing of the incorrectness in the tool. In this paper, we present a debug framework that uses just-in-time (JIT) traces and automated insertion of verification code into the generated RTL to assist in debugging an HLS tool. This framework aids the user by quickly pinpointing the earliest instance of execution mismatch, paired with detailed information on the faulty signal, and the corresponding instruction from the application source. Using CHStone benchmarks, we demonstrate that this technique can significantly reduce bug detection latency: often with zero cycle detection.","PeriodicalId":261246,"journal":{"name":"2015 International Conference on Field Programmable Technology (FPT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125347730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Behavioral-level IP integration in high-level synthesis 高级综合中的行为级IP集成

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393144

Liwei Yang, S. Gurumani, Deming Chen, K. Rupnow

引用次数: 7

An exact MCMC accelerator under custom precision regimes 一个精确的MCMC加速器在定制的精度制度

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393138

Shuanglong Liu, Grigorios Mingas, C. Bouganis

{"title":"An exact MCMC accelerator under custom precision regimes","authors":"Shuanglong Liu, Grigorios Mingas, C. Bouganis","doi":"10.1109/FPT.2015.7393138","DOIUrl":"https://doi.org/10.1109/FPT.2015.7393138","url":null,"abstract":"Markov chain Monte Carlo (MCMC) is one of the most popular and important tools to generate random samples from probability distributions over many variables which occur frequently in Bayesian inference. However, MCMC cannot be practically applied to models with large data sets because of the prohibitive costly likelihood evaluations for each data point. Previous solutions propose to compute the likelihood approximately, e.g. by sub-sampling data or by using custom precision implementations. These methods involve a trade-off between bias in the output and sampling speed; therefore they cannot guarantee unbiased sampling, which is critical in many applications. This paper introduces a novel mixed precision MCMC accelerator for FPGAs, which simulates from the exact probability distribution in contrast to existing approximate MCMC samplers. An auxiliary binary variable is appended to each data point to indicate the corresponding likelihood term evaluation in full or reduced precision. The proposed method guarantees unbiased samples, while the large majority of likelihood computations are performed in reduced precision. Moreover, a tailored FPGA architecture for the algorithm is introduced, and its performance is evaluated using two Bayesian logistic regression case studies of varying complexity: a 2-dimension synthetic problem and MNIST classification with 12-dimension parameters. The achieved speedups over double-precision FPGA designs are 4.21× and 4.76× respectively.","PeriodicalId":261246,"journal":{"name":"2015 International Conference on Field Programmable Technology (FPT)","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134516452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Cryptographic techniques in redundant number systems 冗余数字系统中的密码技术

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393156

J. Motha, A. Bainbridge-Smith, S. Weddell

引用次数: 0

An Implementation of Trax player using programmable SoC 基于可编程SoC的Trax播放器的实现

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393121

A. Kojima

引用次数: 3

An efficient architecture for zero overhead data en-/decryption using reconfigurable cryptographic engine 使用可重构密码引擎实现零开销数据解密的高效架构

2015 International Conference on Field Programmable Technology (FPT) Pub Date : 2015-12-01 DOI: 10.1109/FPT.2015.7393116

Bony H. K. Chen, P. Cheung, P. Cheung, Yu-Kwong Kwok

{"title":"An efficient architecture for zero overhead data en-/decryption using reconfigurable cryptographic engine","authors":"Bony H. K. Chen, P. Cheung, P. Cheung, Yu-Kwong Kwok","doi":"10.1109/FPT.2015.7393116","DOIUrl":"https://doi.org/10.1109/FPT.2015.7393116","url":null,"abstract":"Many applications use encryption to protect data confidentiality, which require decryption before any data processing. Integrating ASIC design of encryption engines and general-purpose processor can yield the best overall performance in program execution as it benefits from low latency hardware engine and high processor memory bandwidth. However, ASIC design is fixed once manufactured, which cannot afford any changes in the implemented cryptographic algorithm. FPGA implementation is attractive in terms of its re-configurability but it is generally much slower than ASIC design. In this demo, we present a novel scheme that can offload the latency of reconfigurable cryptographic engine from the overall execution and define an en-/decryption data interface, which is independent of the underlying encryption algorithms. To verify our proposed scheme, we implemented a FPGA prototype, which integrated our design with OpenRISC on ALTERA DE2i-150 evaluation board. We prove that our proposed architecture can flexibly and efficiently en-/decrypt the data with zero overheads towards overall program execution with careful design. Our case study on SQLite shows that the query execution over a 1GB encrypted database on our implemented system introduces performance overhead ranging from 0% to 14%.","PeriodicalId":261246,"journal":{"name":"2015 International Conference on Field Programmable Technology (FPT)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124758261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3