2015 25th International Conference on Field Programmable Logic and Applications (FPL)最新文献_第9页

Pipelined NoC router architecture design with buffer configuration exploration on FPGA 基于FPGA的流水线NoC路由器架构设计及缓冲配置探索

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7293981

Qi Chen, Qiang Liu

引用次数: 5

A transport-layer network for distributed FPGA platforms 分布式FPGA平台的传输层网络

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7293976

S. Jun, Ming Liu, Shuotao Xu, Arvind

引用次数: 15

Wotan: A tool for rapid evaluation of FPGA architecture routability without benchmarks Wotan:一个无需基准测试即可快速评估FPGA架构可达性的工具

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7294008

Oleg Petelin, Vaughn Betz

{"title":"Wotan: A tool for rapid evaluation of FPGA architecture routability without benchmarks","authors":"Oleg Petelin, Vaughn Betz","doi":"10.1109/FPL.2015.7294008","DOIUrl":"https://doi.org/10.1109/FPL.2015.7294008","url":null,"abstract":"FPGA routing architectures consist of routing wires and programmable switches which together account for a significant portion of the fabric delay and area. Routing architectures have traditionally been evaluated using a full CAD flow with a suite of benchmark circuits. While the results of such a flow can be accurate, CAD tools are often tuned to a specific architecture type and can take a long time to run which prohibits quick exploration of different architectures early in the design process. In this paper we present an alternative approach that quickly estimates routability for a wide range of architectures without the use of benchmark circuits. Our new routability predictor first assigns congestion probabilities to the architecture's routing resources based on demand estimates found via efficient path enumeration through the routing graph. Next, we compute the probabilities of successfully routing different source/sink connections and finally we combine them to assign an overall routability score. We describe our predictor and present routability estimates for a range of 6-LUT and 4-LUT architectures, showing reasonable agreement with routability results from the full VPR CAD flow in much less CPU time.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123765914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Accurate power analysis for near-Vt RRAM-based FPGA 基于近vt随机存储器的FPGA精确功耗分析

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7293982

Xifan Tang, P. Gaillardon, G. Micheli

引用次数: 14

Adaptive MRAM-based CGRAs 基于mram的自适应CGRAs

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7293984

Xiaobin Liu, Tedy Thomas, Alan Boguslawski, R. Tessier

引用次数: 1

Design and simulation tools for Embedded NOCs on FPGAs fpga上嵌入式noc的设计与仿真工具

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7293965

M. Abdelfattah, Andrew Bitar, Ange Yaghi, Vaughn Betz

引用次数: 2

High speed ECC implementation on FPGA over GF(2m) 基于GF(2m)的FPGA高速ECC实现

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7293951

Z. Khan, M. Benaissa

{"title":"High speed ECC implementation on FPGA over GF(2m)","authors":"Z. Khan, M. Benaissa","doi":"10.1109/FPL.2015.7293951","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293951","url":null,"abstract":"High speed Elliptic Curve Cryptography (ECC) implementations on Field Programmable Gate Array (FPGA) are highly desirable for applications requiring high speed cost effective and flexible implementations of public key cryptography. Recently, many binary ECC hardware accelerators have been presented based on the Montgomery point multiplication by exploiting the underlying parallelism of the point multiplication (PM). In this paper, we present a combined Montgomery point multiplication algorithm to achieve low latency ECC point multiplication by using novel pipelined full precision parallel multipliers over GF(2m). We adopt a careful schedule of point operations to achieve low latency and a smart pipelining in the ECC architecture to reduce the critical path delay. Our proposed ECC architecture is implemented on Virtex5 (XCV5LX110) for a fair comparison and on Virtex7 (XC7VX550T) to quantify performance. Our Virtex5 based implementation over GF(2163), consumes 10363 slices, takes only 5.1 μs for an ECC point multiplication with a frequency of 153 MHz, and has a latency of 780 clock cycles. Our Virtex-5 performance outperforms the fastest reported work on the same platform. Our Virtex7 implementation which can compute an ECC PM in 3.50 μs at a frequency of 223 MHz while utilising only 8736 slices is the highest speed implementation reported to date on FPGA.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125656286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24

A study of data partitioning on OpenCL-based FPGAs 基于opencl的fpga数据分区研究

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7293941

Ze-ke Wang, Bingsheng He, Wei Zhang

{"title":"A study of data partitioning on OpenCL-based FPGAs","authors":"Ze-ke Wang, Bingsheng He, Wei Zhang","doi":"10.1109/FPL.2015.7293941","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293941","url":null,"abstract":"A lot of research efforts have been devoted to accelerating relational database applications on FPGAs, due to their high energy efficiency and high throughput. Most of the existing studies are based on hardware description languages (HDLs). Recently, FPGA vendors have started to develop OpenCL SDKs for much better programmability. In this paper, we investigate the performance of relational database applications on OpenCL-based FPGAs. As a start, we study the performance of data partitioning, a core operation widely used in relational databases. Due to random memory accesses, data partitioning is time-consuming and can become a major bottleneck for database operators such as hash join. We start with the state-of-the-art OpenCL implementation which was originally designed for CPUs/GPUs, and find that it suffers from lock overheads and memory bandwidth overheads. To reduce lock overheads, we develop a simple yet efficient multi-kernel approach to leverage two emerging features of Altera OpenCL SDK, namely task kernel and channel. Moreover, on-chip buckets are employed to reduce the number of memory transactions. We further develop a cost model to guide the parameter configuration. We evaluate the proposed design on a recent Altera Stratix V FPGA. Our results demonstrate 1) our cost model can accurately predict the performance of data partitioning under different parameter settings; 2) our proposed multi-kernel approach can achieve 10.7X; speedup over the existing OpenCL implementation. Also, the experiments with three case studies show that the optimized implementations can achieve 4-12X performance improvement over the original implementations.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117039611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 46

Temperature-triggered behavioral IPs HW Trojan detection method with FPGAs 基于fpga的温度触发行为ip木马检测方法

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7294009

Xiaotong Li, Benjamin Carrión Schäfer

{"title":"Temperature-triggered behavioral IPs HW Trojan detection method with FPGAs","authors":"Xiaotong Li, Benjamin Carrión Schäfer","doi":"10.1109/FPL.2015.7294009","DOIUrl":"https://doi.org/10.1109/FPL.2015.7294009","url":null,"abstract":"This works targets the detection of temperature triggered HW Trojans, in particular for third party behavioral IPs (3PBIPs) given in ANSI-C. One of the biggest advantages of C-Based VLSI design is its ability to automatically generate architectures with different trade-offs by only setting different synthesis options. This work uses this property to detect temperature-triggered HW Trojan. A complete design flow is presented. It comprises two main phases: (1) In the first phase, a design space explorer generates micro-architectures with different area vs. power trade-offs automatically for the given behavioral IP. (2) The second phase, maps three of these micro-architectures with different power profiles onto a reconfigurable computing board to create a 3-way redundant system. This system combined with a majority voter scheme is used to detect if a HW Trojan is present in the behavioral IP. Having different power profiles implies that each micro-architecture has a different thermal behavior and thus will trigger the HW Trojan at different time intervals. The outputs of the three designs are compared for discrepancies at regular intervals, allowing our method to therefore exactly pinpoint the exact trigger temperature of the HW Trojan. A case study is presented showing the effectiveness of our method.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126736244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Variable-latency signed addition on FPGAs fpga上的可变延迟签名加法

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7293957

A. Cilardo

引用次数: 6