2015 25th International Conference on Field Programmable Logic and Applications (FPL)最新文献

Limits of FPGA acceleration of 3D Green's Function computation for geophysical applications 地球物理应用中三维格林函数计算的FPGA加速限制

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293942

Nachiket Kapre, J. S. Kumar, P. Gupta, S. Masuti, S. Barbot

引用次数: 0

Generating FPGA accelerators for chemical similarity assessment 生成用于化学相似性评估的FPGA加速器

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293977

Nikolaos S. Alachiotis

{"title":"Generating FPGA accelerators for chemical similarity assessment","authors":"Nikolaos S. Alachiotis","doi":"10.1109/FPL.2015.7293977","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293977","url":null,"abstract":"Numerical measures of similarity/distance between objects represented by binary vectors are common in a wide range of disciplines. Searching in large-scale chemical databases requires billions of comparisons between molecules that are represented by binary fingerprints to capture the atomic structure. The performance bottleneck here is the enumeration of set bits in vectors (population count). Due to the discrete representation, similarity measures between binary fingerprints should fit well to FPGAs. We present an architecture to accelerate binary similarity assessment, evaluate various design points, and compare performance to highly optimized CPU and GPU implementations. We implement an RTL generation software, SimGenRTL, to generate accelerators of various sizes based on the proposed architecture. We find that accelerators with fewer and wider population counters allow better distribution of the hardware resources, outperforming significantly accelerators with more and narrower bit-enumeration components. SimGenRTL is available for download to allow rapid design space exploration of the computational core ahead of a full custom system implementation.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122952811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

SPINE: From C loop-nests to highly efficient accelerators using Algorithmic Species 脊椎:从C循环巢到使用算法物种的高效加速器

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7294015

M. Wijtvliet, Shakith Fernando, H. Corporaal

{"title":"SPINE: From C loop-nests to highly efficient accelerators using Algorithmic Species","authors":"M. Wijtvliet, Shakith Fernando, H. Corporaal","doi":"10.1109/FPL.2015.7294015","DOIUrl":"https://doi.org/10.1109/FPL.2015.7294015","url":null,"abstract":"In modern embedded systems, heterogeneous architectures are crucial in achieving desired performance requirements under area and energy constraints. Many of these systems combine a multi-processor system-on-chip and a Field Programmable Gate Array to enable hardware acceleration. Although the introduction of High-Level Synthesis significantly reduced the complexity of utilizing these systems, a programmer is still required to have expert knowledge of both the High-Level Synthesis tool and the target hardware and to perform time consuming manual iterations to achieve efficient implementations. In this paper we present SPINE, a design flow for automatic generation of efficient hardware accelerators based on Algorithmic Species. SPINE allows the designer to focus on the algorithm by automatically applying hardware specific optimizations and parallelization techniques to the design. As a case study, we present a design space exploration of nine different loop-nests used in image processing kernels and show how SPINE rapidly generates multiple area-performance trade-offs. Furthermore, we compare our results the state of the art and show that SPINE is a promising direction for accelerator generation as the average performance and area improvement with SPINE are respectively 107% and 75% over the state of the art.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121506233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A fully pipelined kernel normalised least mean squares processor for accelerated parameter optimisation 用于加速参数优化的全流水线核归一化最小均方处理器

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293952

Nicholas J. Fraser, Duncan J. M. Moss, JunKyu Lee, Stephen Tridgell, C. Jin, P. Leong

{"title":"A fully pipelined kernel normalised least mean squares processor for accelerated parameter optimisation","authors":"Nicholas J. Fraser, Duncan J. M. Moss, JunKyu Lee, Stephen Tridgell, C. Jin, P. Leong","doi":"10.1109/FPL.2015.7293952","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293952","url":null,"abstract":"Kernel adaptive filters (KAFs) are online machine learning algorithms which are amenable to highly efficient streaming implementations. They require only a single pass through the data during training and can act as universal approximators, i.e. approximate any continuous function with arbitrary accuracy. KAFs are members of a family of kernel methods which apply an implicit nonlinear mapping of input data to a high dimensional feature space, permitting learning algorithms to be expressed entirely as inner products. Such an approach avoids explicit projection into the feature space, enabling computational efficiency. In this paper, we propose the first fully pipelined floating point implementation of the kernel normalised least mean squares algorithm for regression. Independent training tasks necessary for parameter optimisation fill L cycles of latency ensuring the pipeline does not stall. Together with other optimisations to reduce resource utilisation and latency, our core achieves 160 GFLOPS on a Virtex 7 XC7VX485T FPGA, and the PCI-based system implementation is 70× faster than an optimised software implementation on a desktop processor.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125718389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Software-in-the-Loop simulation of embedded control applications based on Virtual Platforms 基于虚拟平台的嵌入式控制应用软件在环仿真

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7294020

Stephan Werner, Leonard Masing, Fabian Lesniak, J. Becker

{"title":"Software-in-the-Loop simulation of embedded control applications based on Virtual Platforms","authors":"Stephan Werner, Leonard Masing, Fabian Lesniak, J. Becker","doi":"10.1109/FPL.2015.7294020","DOIUrl":"https://doi.org/10.1109/FPL.2015.7294020","url":null,"abstract":"One challenge in developing complex software for embedded systems is the missing option of rapid prototyping in early stages of the development cycle. In this paper we present the use of the High Level Simulation Framework “Open Virtual Platforms” (OVP) for Software-in-the-Loop simulation of embedded control applications. Therefore, we investigate and evaluate different methods allowing the data exchange between the simulated platform and the host machine running the simulation environment. The insights we gain are used to design peripherals which appear to the simulated processor system like devices available on the targeted hardware platform and allow the access to files stored on the host machine on one hand, and the communication with hardware devices connected to the host on the other hand. In both cases the cross-compiled application code for the targeted embedded platform including the operating system (OS) and the hardware abstraction layer (HAL) can be executed by the virtual platform (VP) without any modifications. Additionally, we introduce a method for controlling the synchronization of OVP with the host, which can be used to either run simulations in fast motion mode, or to collaborate with hardware devices or other applications. The approach is verified with two use cases: (1) a motor control application processing data by accessing files and (2) an image processing application interacting with real hardware devices directly coupled with the virtual platform.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125993229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

A software configurable coprocessor-based state-space controller 一种基于协处理器的软件可配置状态空间控制器

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293752

Aaron Mills, Pei Zhang, Sudhanshu Vyas, Joseph Zambreno, Phillip H. Jones

引用次数: 6

An FPGA implementation of a phylogenetic tree reconstruction algorithm using an alternative second-pass optimization 一个系统发育树重建算法的FPGA实现，使用可选的第二遍优化

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293973

Henry Block, T. Maruyama

引用次数: 1

Power-efficient range-match-based packet classification on FPGA 基于距离匹配的高效FPGA分组分类

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293937

Yun Qu, V. Prasanna

引用次数: 0

A run time interpretation approach for creating custom accelerators 用于创建自定义加速器的运行时解释方法

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293996

Sen Ma, Zeyad Aklah, D. Andrews

{"title":"A run time interpretation approach for creating custom accelerators","authors":"Sen Ma, Zeyad Aklah, D. Andrews","doi":"10.1109/FPL.2015.7293996","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293996","url":null,"abstract":"The world of software development has the notion of just-in-time compilation, run time binary translation, and language interpretation. These dynamic run time techniques support increased code portability and designer productivity. There are no such equivalences to increase the productivity or portability of creating new hardware components within Field Programmable Gate Arrays (FPGAs). Instead, creating a new hardware component requires hardware design skills and the overhead of running through synthesis, place and route. If a change is made to even a single line of code, the synthesis, place and route steps must be repeated. In this paper we present a new approach that allows hardware accelerators to be built and run using compilation and run time interpretation. Our results show the approach can enable software programmers without any hardware skills to create hardware accelerators at productivity levels consistent with software development and compilation. The same accelerator can be compiled 100× faster than synthesis. Even though the approach is focused on productivity, our observed performance results are promising. Our initial application test cases show the same accelerator written by a software programmer and synthesized through Vivado HLS or written using our DSL and compiled within our approach achieves equivalent performance.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134408267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

A scalable pipelined architecture for biomimetic vision sensors 仿生视觉传感器的可扩展流水线架构

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293935

D. Llamocca, Brian K. Dean

引用次数: 2