2015 25th International Conference on Field Programmable Logic and Applications (FPL)最新文献_第2页

Data-triggered breakpoint for in-circuit debug without re-implementation 数据触发的断点用于不重新实现的在线调试

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293997

Y. Tamiya, Yoshinori Tomita, Toshiyuki Ichiba, Kaoru Kawamura

{"title":"Data-triggered breakpoint for in-circuit debug without re-implementation","authors":"Y. Tamiya, Yoshinori Tomita, Toshiyuki Ichiba, Kaoru Kawamura","doi":"10.1109/FPL.2015.7293997","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293997","url":null,"abstract":"In this paper we propose a new breakpoint mechanism, which improves controllability of in-circuit debug. It monitors data packets transmitted on the interface port of the target hardware, and triggers a breakpoint when a specified packet is detected among them in realtime. Regarding a data packet as a series of data sequences, we employ an efficient data sequence matching circuit, which is general purpose and is not restricted to specific protocols or applications. Owing to linearity of CRC (Cyclic Redundancy Check) and co-operation with a software debugger, that matching method is implemented with a simple in-circuit debug module, and achieves at-speed and realtime detection of specified data sequences. Moreover, changing breakpoint conditions does not require hardware re-implementation, but requires just modifying values of data registers inside the debug module. We expect this brings verification operators enormous reduction of both efforts and TAT (Turn-Around-Time) for in-circuit debug. Our experimental results show our proposed method can be implemented in an efficient hardware with small area overheads, and can work with enough accuracy and speed for practical use.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133729532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-Level-Synthesis extensions for scalable Single-Chip Many-Accelerators on FPGAs fpga上可扩展的单芯片多加速器的高级合成扩展

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293992

D. Diamantopoulos, S. Xydis, K. Siozios, D. Soudris

{"title":"High-Level-Synthesis extensions for scalable Single-Chip Many-Accelerators on FPGAs","authors":"D. Diamantopoulos, S. Xydis, K. Siozios, D. Soudris","doi":"10.1109/FPL.2015.7293992","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293992","url":null,"abstract":"Accelerator-coupled systems have been introduced as a promising architectural paradigm that can boost performance and improve power of general-purpose computing platforms. This research focuses on the accelerators' scalability problem due to resource under-utilization in FPGA-based accelerator-coupled platforms. By recognizing that static memory allocation the de-facto memory management mechanism supported by modern design techniques and synthesis tools forms the main source of memory-induced under-utilization, i.e. leading up to 75% of dark silicon, we propose the development of a) a Single-Chip Many-Accelerator (SCMA) architecture that reduces energy budget by providing high-throughput processing nodes hooked under the same low-latency FPGA die and b) a novel design framework that extends conventional RTL and High Level Synthesis (HLS) design flows with dynamic memory management (DMM) features to leverage scalability by enabling accelerators to dynamically adapt their allocated memory to the runtime memory requirements, thus maximizing the overall accelerator count through effective sharing of FPGA's memories resources. By applying these novel techniques in the state-of-art Vivado-HLS tool, we managed to increase accelerator density up to 3.8× for a Xilinx Ultrascale device and deliver architecture solutions that trade-off per-accelerator latency overhead (1.2×- 19.9×) with overall system's throughput (2.6×- 23.1×) and performance-per-watt (0.09×- 21.7×).","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130991221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

AmBRAMs - An analysis tool, method and framework for advanced measurements and reliability assessments on modern nanoscale FPGAs AmBRAMs -一种分析工具、方法和框架，用于现代纳米级fpga的先进测量和可靠性评估

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293963

P. Pfeifer

引用次数: 0

A variable length hash method for faster short read mapping on FPGA 可变长度哈希方法在FPGA上更快的短读映射

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293938

Y. Sogabe, T. Maruyama

引用次数: 3

An efficient many-core architecture for Elliptic Curve Cryptography security assessment 椭圆曲线密码安全评估的高效多核体系结构

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293950

Marco Indaco, Fabio Lauri, Andrea Miele, Pascal Trotta

引用次数: 4

Rapid prototyping and Design Space Exploration methodologies for many-accelerator systems 多加速器系统的快速原型设计和设计空间探索方法

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293990

Efstathios Sotiriou-Xanthopoulos, S. Xydis, K. Siozios, G. Economakos, D. Soudris

{"title":"Rapid prototyping and Design Space Exploration methodologies for many-accelerator systems","authors":"Efstathios Sotiriou-Xanthopoulos, S. Xydis, K. Siozios, G. Economakos, D. Soudris","doi":"10.1109/FPL.2015.7293990","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293990","url":null,"abstract":"The ever-growing design complexity of modern embedded systems and the need for lower energy consumption have lead to design techniques which target to bridge the gap between the designer's productivity and the design complexity. In particular, Virtual Prototyping enables the system modeling and simulation in multiple abstraction levels, while the automated Design Space Exploration (DSE) targets to find optimized design solutions in a reasonable time. However, there is the need for more efficient techniques for prototyping and co-simulation, as the rapid simulation has become a stringent requirement. In addition, as emerging heterogeneous architectures expose even higher design complexity, typical DSE techniques may not achieve high-quality design solutions. Towards this direction, the proposed design flow introduces (a) a set of prototyping techniques which target to faster but accurate simulation, also supporting the system co-simulation with other environments, and (b) a number of DSE methodologies for high-complexity computation and communication architectures.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115969848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Domain-specific optimisation for the high-level synthesis of CellML-based simulation accelerators 针对基于cellml的仿真加速器的高级合成的领域特定优化

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7294019

J. Oppermann, A. Koch, Ting-Rong Yu, O. Sinnen

{"title":"Domain-specific optimisation for the high-level synthesis of CellML-based simulation accelerators","authors":"J. Oppermann, A. Koch, Ting-Rong Yu, O. Sinnen","doi":"10.1109/FPL.2015.7294019","DOIUrl":"https://doi.org/10.1109/FPL.2015.7294019","url":null,"abstract":"The simulation of biomedical models often requires the numerical integration of ordinary differential equation systems, a computationally intensive task that can be accelerated well by deeply-pipelined FPGA-based accelerators. Since the main design target is throughput, larger FPGA devices can easily be exploited by scaling-up the number of parallel datapath instances on a chip. To this end, reducing the area of each datapath becomes a key optimisation. High-level synthesis can be employed to generate custom simulation accelerators from standardised cell descriptions in CellML. In this work, we improve this process by inserting LLVM into the flow to pre-optimise the simulation models generated from CellML for hardware synthesis. This is achieved not only by the selective application of general-purpose optimisation passes, but also by adding new domain-specific optimisations, including unsafe floating-point transformations, to the optimisation flow. We investigate their effect on the quality-of-results and show that a novel strategy using our optimisations outperforms standard strategies, such as LLVM's -Oz (aggressive size reduction), when applied for hardware synthesis in 99 out of 146 example models. Our approach, which reduces area by up to 25%, leads to the smallest implementations for four models examined in detail, and allows a particularly complex cell model to fit on the target FPGA device for the first time.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129508452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

rrBox: A remote dynamically reconfigurable network processing middlebox rrBox:远程动态可重构网络处理中间盒

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293971

Tze Hon Tan, C. Y. Ooi, M. N. Marsono

引用次数: 5

A technology mapper for depth-constrained FPGA logic cells 深度约束FPGA逻辑单元的技术映射器

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7294014

Zhenghong Jiang, Grace Zgheib, C. Y. Lin, D. Novo, Zhihong Huang, Liqun Yang, Haigang Yang, P. Ienne

{"title":"A technology mapper for depth-constrained FPGA logic cells","authors":"Zhenghong Jiang, Grace Zgheib, C. Y. Lin, D. Novo, Zhihong Huang, Liqun Yang, Haigang Yang, P. Ienne","doi":"10.1109/FPL.2015.7294014","DOIUrl":"https://doi.org/10.1109/FPL.2015.7294014","url":null,"abstract":"In the last decade, progress in logic synthesis has brought about new advantageous circuit representations. These representations, such as And-Inverter Graphs in the ubiquitous open-source synthesizer ABC, have inspired new designs of Field Programmable Gate Arrays (FPGAs), which, instead of using Look-Up Tables (LUTs), mimic the topology of the circuit representation in the basic logic cells. More recent examples are Majority-Inverter Graphs, another uniform representation which has triggered considerable interest in synthesis and which naturally suggests new logic cells. Yet, in this paper we observe how naïvely adapting technology mapping solutions for classic LUT-based FPGAs to these new architectures incurs severe shortcomings. The key issue is that LUTs are inherently input-constrained (the logic function they implement is irrelevant) and have generally a single output; on the other hand, logic cells made of uniform networks of some fundamental logic function (e.g., And-Invert) are constrained in terms of logic depth and multiple outputs are an integral feature. We introduce novel and effective solutions to address these differences; the result is a highly versatile mapper - thus enabling further research in these new architectures - with a significantly better performance than what is described in literature for one such architecture. Specifically, when we compare with the state of the art on one sample architecture, we obtain a significant decrease in area (on average 18% over several benchmarks) while also improving slightly the critical path (a reduction of 3%).","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"54 84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122295580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Hoplite: Building austere overlay NoCs for FPGAs 重装步兵:为fpga构建严格的覆盖noc

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293956

Nachiket Kapre, J. Gray

{"title":"Hoplite: Building austere overlay NoCs for FPGAs","authors":"Nachiket Kapre, J. Gray","doi":"10.1109/FPL.2015.7293956","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293956","url":null,"abstract":"Customized unidirectional, bufferless, deflection-routed torus networks can outperform classic, bidirectional, buffered mesh networks for single-flit-oriented FPGA applications by as much as 1.5× (best achievable throughputs for a 10×10 system) or 2.5× (allocating same FPGA resources to both NoCs) for uniform random traffic. We present Hoplite, an efficient, lightweight, fast FPGA overlay NoC that is designed to be small and compact by (1) eliminating input buffers, and (2) reducing the cost of switch crossbar that have traditionally limited speeds and imposed heavy resource costs in conventional FPGA overlay NoCs. We implement bufferless deflection routing cheaply, requiring the generation of only output multiplexer controls and no backpressure handshakes. Additionally, we use directional channels that help reduce crossbar cost by restricting the number of inputs to the crossbar to three instead of four. When compared to buffered mesh switches, FPGA-based deflection routers are ≈3.5× smaller (HLS-generated switch) and 2.5× faster (clock period) for 32b payloads. In a separate experiment, we hand-crafted a prototype RTL version of our switch with RLOCS that requires only 60 LUTs and 100 FFs per router and runs at 2.9 ns.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132983857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 111