2015 25th International Conference on Field Programmable Logic and Applications (FPL)最新文献

{"title":"Efficient data-stream management for shared-memory many-core systems","authors":"Nuno Neves, P. Tomás, N. Roma","doi":"10.1109/FPL.2015.7293960","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293960","url":null,"abstract":"The design of most high-performance and heterogeneous processing platforms is usually solely focused on the computational part, while neglecting the power/performance impact of the data-management infrastructures. Moreover, such systems often struggle to achieve their potential performance when applications require fetching data with complex memory access patterns. To overcome these issues, a energy-efficient stream-based data-management infrastructure is herein proposed, relying on a novel tree-based descriptor specification. Such descriptors are decoded by a Descriptor Tree Controller (DTC) architecture, which allows simple and efficient management of arbitrarily complex memory access patterns. Moreover, a Stream Management Engine (SME) ensures energy-efficient data-reutilization through the application of automatic stream rerouting, splitting and merging techniques. The obtained results show that the proposed DTC architecture is capable of a highly efficient complex data-pattern generation, while significantly reducing the size occupied by the pattern description, when compared with state-of-the-art approaches. By also enabling the deployment of data-reuse techniques, a reduction of up to 85× in the number of accesses to the main shared memory is achieved, resulting in a decrease as high as 475× in the observed energy consumption.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"155 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128694680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Towards heterogeneous solvers for large-scale linear systems","authors":"Stylianos I. Venieris, Grigorios Mingas, C. Bouganis","doi":"10.1109/FPL.2015.7293751","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293751","url":null,"abstract":"Applying Linear Regression to systems with a massive amount of observations, a scenario which is becoming increasingly common in the era of Big Data, poses major algorithmic and computational challenges. This paper proposes a novel high-performance FPGA-based architecture for large-scale Linear Regression problems as well as a heterogeneous system comprising the custom FPGA architecture, an enhanced GPU module and a multi-core CPU for addressing the aforementioned problem. The system adaptively assigns Linear Regression workloads to the three computing devices to minimise runtime. The device with the highest performance is chosen based on an analytical framework, as well as the workload's size and structure. A quantitative comparison with existing FPGA, GPU and multi-core CPU designs yields speed-ups of up to 18.07×, 32.67× and 25.84× respectively.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116040721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ultra low latency dataflow renderer","authors":"Sebastian Friston, A. Steed, S. Tilbury, G. Gaydadjiev","doi":"10.1109/FPL.2015.7293974","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293974","url":null,"abstract":"Reconfigurable hardware has been used before for low latency image synthesis. These are typically low level implementations with tight vertical integration. For example the apparatus of both Regan et al and Ng et al had the tracker driven by the same device performing the rendering. Reconfigurable hardware combined with the dataflow programming model can make application specific rendering hardware cost effective. Our sprite renderer has comparable scope to both prior examples, but our dataflow graph can be adapted to other use cases with an effort comparable to GPU shader programming.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"47 35","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113957797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Compact dual block AES core on FPGA for CCM Protocol","authors":"João Carlos Resende, R. Chaves","doi":"10.1109/FPL.2015.7293948","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293948","url":null,"abstract":"This paper presents a compact and FPGA based implementation of the AES encryption standard, specifically designed for processing two independent 128-bit input blocks in feedback modes. This configuration is particularly focused on the Counter with CBC-MAC Protocol, but can also be adapted to other AES based encryption-authentication protocols requiring the processing of two independent data streams. Most of the state of the art solutions implementing CCMP consider large datapaths, sometimes with separated encryption datapaths for the different data streams, leading to low resource efficiency. The work herein proposed suggests that with adequate FPGA component usage and with proper data scheduling a very compact and efficient dual AES core can be derived particularly on FPGAs. Overall, the proposed structure allows for a throughput of 1.7Gbps while achieving a Throughput/Slice efficiency of 24.22 Mbps/Slice, 47% higher than the existing related state of the art.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128065332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Building a distributed key-value store with FPGA-based microservers","authors":"Z. István, David Sidler, G. Alonso","doi":"10.1109/FPL.2015.7293967","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293967","url":null,"abstract":"Energy efficiency is one of the major challenges in datacenters, and a promising way to tackle it are microservers. These scaled down machines with smaller CPUs, less peripherals and tighter integration improve energy efficiency, but often at the expense of lower performance. In this work we explore the tailoring of standard software components to specialized hardware as a way to get the energy efficiency of microservers without compromising performance. Our specialized microserver implements memcached, a common component in many web stacks, on a cluster of FPGAs. The design explores aspects such as pipelining techniques, tight integration with the network stack, dealing with the memory bottleneck, and shows how to build a complete system out of individual microservers. To our knowledge this is the first stand-alone FPGA-based solution that can be used as a drop-in replacement for the software version. Beyond the per-node performance, in this demo we focus on the replication and the integration aspects of our system. We run a common benchmark on a PostgreSQL database with a two-node deployment of FPGAs acting as a cache for query results.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129753241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fast FPGA system for microarchitecture optimization on synthesizable modern processor design","authors":"Libo Huang, Yongwen Wang, Q. Dou, Chengyi Zhang, Caixia Sun, Chao Xu","doi":"10.1109/FPL.2015.7294005","DOIUrl":"https://doi.org/10.1109/FPL.2015.7294005","url":null,"abstract":"Microarchitecture optimization for processor design is a must to achieve target system performance. Provided the register transfer level (RTL) model in real chip design, this paper proposes MOFPGA system, which uses field programmable gate array (FPGA) prototyping as an effective method for fine-grain microarchitecture optimization. It is a fast, reconfigurable, and visible platform with zero impact on the performance of the monitored processor. MOFPGA implements a complete computing platform equipped with a modern out-of-order processor and is able to achieve 60 MHz processor frequency. Besides general FPGA implementation techniques such as multi-port SRAM design and gate-clock conversion, extensive optimization efforts are done to improve the FPGA performance of mapping such a large core. To our knowledge, MOFPGA is the first published FPGA system that implements a modern out-of-order processor running at such high frequency and can report the real SPEC CPU2000 evaluation results.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131399955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FPGA implementation to estimate the number of endmembers in hyperspectral images","authors":"Carlos González, D. Mozos, S. López, R. Sarmiento","doi":"10.1109/FPL.2015.7293936","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293936","url":null,"abstract":"Spectral unmixing is an important task for remotely sensed hyperspectral data exploitation. It amounts the identification of pure spectral signatures (endmembers) in the data, and the estimation of the abundance of each endmember in each (possibly mixed) pixel. A challenging problem in spectral unmixing is how to determine the number of endmembers in a given scene. For this purpose, many algorithms have been proposed in the recent literature, being the estimation of the Virtual Dimensionality (VD) of the hyperspectral image and the hyperspectral signal subspace estimator (HySime) two of the most popular choices. Unfortunately, the high dimensionality of the hyperspectral data provided by modern sensors as well as the inherent computational complexity clearly make the use of these algorithms prohibitive for applications under real-time or near real-time constraints. Hence, the utilization of high performance computing platforms in order to accelerate the process of unmixing a hyperspectral image becomes mandatory for such scenarios. Reconfigurable hardware solutions such as field programmable gate arrays (FPGAs) have consolidated during the last years as one of the preferred choices for the fast processing of hyperspectral remotely sensed images due to their advantages over other high performance computing systems, such as clusters of computers, multicore processors and/or graphical processing units (GPUs). This paper uncovers two FPGA-based architectures for accelerating the process of estimating the number of endmembers that constitute a hyperspectral image according to the VD and the HySime algorithms. The proposed methods have been implemented on a Virtex-7 XC7VX690T FPGA and tested using real hyperspectral data collected by NASAs Airborne Visible Infra-Red Imaging Spectrometer (AVIRIS) over the Cuprite mining district in Nevada and the World Trade Center in New York. Experimental results demonstrate that the VD implementation exhibits real-time performance while the HySime implementation exhibits near real-time performance. Both implementations significantly outperform a software version, which makes our reconfigurable system appealing for onboard hyperspectral data processing.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131640225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A resilient, flash-free soft error mitigation concept for the CBM-ToF read-out chain via GBT-SCA","authors":"A. Oancea, C. Stüllein, J. Gebelein, U. Kebschull","doi":"10.1109/FPL.2015.7293999","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293999","url":null,"abstract":"The ToF detector read-out chain of the upcoming CBM experiment at FAIR will be equipped with FPGA-based read-out boards (ROBs), which are going to be operated in a radiation environment. Flash-based FPGAs are not an option for this experiment due to their low total ionizing dose limit compared to SRAM-based FPGAs, and therefore the latter is foreseen for the ROBs. Consequently, precautions against soft errors in the configuration memories of the FPGAs need to be taken to keep the chain operational. The proposed approach merges on-chip single upset correction with external intervention for multiple-bit upsets and resets. The external intervention is going to be implemented via the control path of the chain through the GBT-SCA, which offers a JTAG interface, as well as interrupt-capable GPIOs among other features. Thus, the use of the GBT-SCA enables an event-driven configuration upset mitigation concept, while being itself radiation hardened by design. Conventional blind configuration scrubbing would cause a continuous load on the control path, while the selective frame scrubbing reduces this load significantly. The concept has been validated in beamtests conducted at COSY, FZ Juelich, Germany. The concept, the beamtest results and limitations of the implementation are presented and discussed in this paper.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115620308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enhancing stochastic computations via process variation","authors":"R. Duarte, M. Véstias, H. Neto","doi":"10.1109/FPL.2015.7293962","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293962","url":null,"abstract":"Stochastic computing has emerged as a computational paradigm that offers arithmetic operators with high-performance, compact implementations and robust to errors by producing approximate results. This work addresses two of the major limitations for its implementation which affects its accuracy: the correlation between stochastic bitstreams and the unobserved signal transitions. A novel implementation of stochastic arithmetic building-blocks is proposed to improve the quality of the results. It relies on Self-Timed Ring-Oscillators to produce different clock signals with different clock frequencies, by taking advantage of the influence of process variation in the timing of the logic elements on the FPGA. This work also presents an automated test platform for stochastic systems, which was used to evaluate the impact of the proposed enhancements. Tests were performed to compare both proposed and typical implementations, on reconfigurable devices with 28nm and 60nm fabrication processes. Finally, presented results demonstrate that the proposed architectures subjected to the impact of process variation improve the quality of the results.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129043208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Energy optimization of FPGA-based stream-oriented computing with power gating","authors":"Mohammad Hosseinabady, J. Núñez-Yáñez","doi":"10.1109/FPL.2015.7293946","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293946","url":null,"abstract":"In this paper, we propose a technique to improve the energy efficiency of FPGA devices by exploiting power gating during idle periods in streaming applications. The main idea is to shuffle idle periods during application execution so that the energy and timing overheads of turning the FPGA on and off can become acceptable. A key requirement is that fast FPGA-based accelerators are available and that the application follows a repetitive nature of execution. In this case, the accelerators work on a successive computing mode to accumulate the idle intervals in different iterations in order to make power gating feasible. Streaming on demand applications which are ubiquitous in embedded and portable devices are very good candidates to benefit from this technique. A case study is presented based on an MP3 player as the streaming application which shows up to 52.9% energy reduction.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124188733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}