2015 25th International Conference on Field Programmable Logic and Applications (FPL)最新文献_第4页

Ultra-fast NoC emulation on a single FPGA 在单个FPGA上的超快速NoC仿真

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7294021

Thiem Van Chu, Shimpei Sato, Kenji Kise

引用次数: 23

Hybrid breadth-first search on a single-chip FPGA-CPU heterogeneous platform 单片FPGA-CPU异构平台上的混合宽度优先搜索

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293939

Yaman Umuroglu, Donn Morrison, Magnus Jahre

{"title":"Hybrid breadth-first search on a single-chip FPGA-CPU heterogeneous platform","authors":"Yaman Umuroglu, Donn Morrison, Magnus Jahre","doi":"10.1109/FPL.2015.7293939","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293939","url":null,"abstract":"Large and sparse small-world graphs are ubiquitous across many scientific domains from bioinformatics to computer science. As these graphs grow in scale, traversal algorithms such as breadth-first search (BFS), fundamental to many graph processing applications and metrics, become more costly to compute. The cause is attributed to poor temporal and spatial locality due to the inherently irregular memory access patterns of these algorithms. A large body of research has targeted accelerating and parallelizing BFS on a variety of computing platforms, including hybrid CPU-GPU approaches for exploiting the small-world property. In the same spirit, we show how a single-die FPGA-CPU heterogeneous device can be used to leverage the varying degree of parallelism in small-world graphs. Additionally, we demonstrate how dense rather than sparse treatment of the BFS frontier vector yields simpler memory access patterns for BFS, trading redundant computation for DRAM bandwidth utilization and faster graph exploration. On a range of synthetic small-world graphs, our hybrid approach performs 7.8× better than software-only and 2× better than accelerator-only implementations. We achieve an average traversal speed of 172 MTEPS (millions of traversed edges per second) on the ZedBoard platform, which is more than twice as effective as the best previously published FPGA BFS implementation in terms of traversals per bandwidth.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"391 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131753729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 49

Using island-style bi-directional intra-CLB routing in low-power FPGAs 在低功耗fpga中使用岛式双向clb内路由

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293945

Oluseyi A. Ayorinde, He Qi, Yu Huang, B. Calhoun

{"title":"Using island-style bi-directional intra-CLB routing in low-power FPGAs","authors":"Oluseyi A. Ayorinde, He Qi, Yu Huang, B. Calhoun","doi":"10.1109/FPL.2015.7293945","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293945","url":null,"abstract":"Increased clustering in Field Programmable Gate Arrays (FPGAs) has shifted a larger fraction of the overall routing load into the configurable logic blocks (CLBs), reducing usage of the costly global interconnect. However, increases in CLB size introduce additional overheads inside CLBs, which can limit the savings gained by minimizing the global interconnect use, motivating more efficient intra-CLB routing. This paper explores different topologies for the intra-CLB connectivity and identifies how the optimal local-CLB interconnect changes for different FPGA architecture and circuit parameters. This work compares area, delay, and energy for two intra-CLB topologies: multiplexer-based routing and island-style bi-directional routing, similar to the global FPGA interconnect, but used inside the CLB (which we call a mini-FPGA). The mini-FPGA style of local CLB interconnect prove to be favorable for minimum-energy operation, as they can reduce transistor count by as much as 62%, and consume as much as 77.9% less energy. Multipexer-based CLBs have performance benefits by reducing delays by almost 3×. Multiplexer-based CLBs can consume less energy at nominal voltages, but only if additional measures are taken to limit power consumption in the multiplexers. A 130-nm CMOS test chip confirms that simulation results track measured data for mini-FPGA CLBs.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123355474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2 采用超低功耗可重构加速器CMA-SOTB-2的7MOPS/柠檬电池图像处理演示

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293964

K. Masuyama, Yu Fujita, Hayate Okuhara, H. Amano

引用次数: 3

High-level FPGA logic synthesis from .NET programs for software developers 高级FPGA逻辑合成从。net程序的软件开发人员

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293968

Zoltan Lehoczky, Richard Toth, Krisztian Somogyi

引用次数: 0

Significant papers from the first 25 years of the FPL conference FPL会议前25年的重要论文

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293747

P. Leong, H. Amano, J. Anderson, K. Bertels, João MP Cardoso, O. Diessel, G. Gogniat, M. Hutton, JunKyu Lee, W. Luk, P. Lysaght, M. Platzner, V. Prasanna, T. Rissa, C. Silvano, Hayden Kwok-Hay So, Yu Wang

引用次数: 1

Fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference 用于概率推理的顺序树重加权信念传播的快速分层实现

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293934

Skand Hurkat, Jungwook Choi, E. Nurvitadhi, José F. Martínez, Rob A. Rutenbar

引用次数: 8

Data protection using recursive inverse function 使用递归逆函数的数据保护

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293978

T. Xu, Hongxiang Gu, M. Potkonjak

{"title":"Data protection using recursive inverse function","authors":"T. Xu, Hongxiang Gu, M. Potkonjak","doi":"10.1109/FPL.2015.7293978","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293978","url":null,"abstract":"Data security and privacy have emerged to become an important issue in various types of applications. Although many cryptographic cyphers are proposed to leverage the issue, they normally suffer from the problems of either requiring large power/bandwidth consumption or employing linear system which is easy to break. To solve the problem of traditional cyphers, we have proposed a new hardware security primitive: recursive inverse function (RIF) designed on the field-programmable gate array (FPGA). The RIF takes advantage of a pair of inverse functions, building a recursive scheme for message encryption and decryption. The inverse functions are defined as a pair of functions where each function implements a mapping being inverse to the mapping of the other function. On the top of it, the recursive structure guarantees the input-output mapping to be statistically extremely hard to predict. The RIF can be easily implemented using hierarchical lookup-table (LUT) structures with low delay and power overhead. Using our proposed RIF structure, we have demonstrated how the RIF can be incorporated into a processor design to enable the data protection. Finally, we implement our scheme on a Xilinx Spartan-6 FPGA device to analyze the performance and the overhead.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114164938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

FPGA-based all-digital Software Defined Radio receiver 基于fpga的全数字软件无线电接收机

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293993

André Prata, Arnaldo S. R. Oliveira, N. Carvalho

引用次数: 3

A portable open-source controller for safe Dynamic Partial Reconfiguration on Xilinx FPGAs Xilinx fpga上安全动态部分重构的便携式开源控制器

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7294002

S. Carlo, P. Prinetto, Pascal Trotta, J. Andersson

引用次数: 10