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2015 25th International Conference on Field Programmable Logic and Applications (FPL)最新文献

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FPGA-based all-digital transmitters 基于fpga的全数字发射机
2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293995
R. Cordeiro, Arnaldo S. R. Oliveira, J. Vieira
{"title":"FPGA-based all-digital transmitters","authors":"R. Cordeiro, Arnaldo S. R. Oliveira, J. Vieira","doi":"10.1109/FPL.2015.7293995","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293995","url":null,"abstract":"This paper presents the architecture and implementation of an FPGA-based all digital transmitter for wireless radio communications. These transmitters allow a greater degree of flexibility for the carrier frequency, signal bandwidth and the use of simultaneous multiple-standards. Latest advances in the state-of-the-art in this emerging area are presented as well as the remaining issues to be solved and the proposed architecture to address some them.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128938124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Greedy approach based heuristics for partitioning SpMxV on FPGAs 基于贪心方法的fpga上SpMxV分区启发式算法
2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293988
Jiasen Huang, Weina Lu, Junyan Ren
{"title":"Greedy approach based heuristics for partitioning SpMxV on FPGAs","authors":"Jiasen Huang, Weina Lu, Junyan Ren","doi":"10.1109/FPL.2015.7293988","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293988","url":null,"abstract":"To eliminate the overhead of zero padding in sparse matrix-vector multiplication (SpMxV), prior works have been focusing on partitioning a sparse matrix into row vectors sets (RVS's) or sub-matrices. Nevertheless, performance degraded still due to the sparsity pattern of a sparse matrix. In this paper, we propose a heuristics, called recursive merging, which uses greedy approach to recursively merge those row vectors of nonzeros in a matrix into the RVS's, such that each set included is ensured a local optimal solution. For ten uneven benchmark matrices from the University of Florida Sparse Matrix Collection, our proposed partitioning algorithm is always identified as the method with the highest mean density (over 96%). An average speedup of 249X is thus achieved for all these ten matrices when 32 processors are allocated for implementation SpMxV on XC7V485T FPGAs.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115103756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Scheduling-aware interconnect synthesis for FPGA-based Multi-Processor Systems-on-Chip 基于fpga的多处理器片上系统的调度感知互连综合
2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293989
E. Fusella, A. Cilardo, A. Mazzeo
{"title":"Scheduling-aware interconnect synthesis for FPGA-based Multi-Processor Systems-on-Chip","authors":"E. Fusella, A. Cilardo, A. Mazzeo","doi":"10.1109/FPL.2015.7293989","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293989","url":null,"abstract":"Multi-Processor System-on-Chip (MPSoC) applications can rely today on a very large spectrum of interconnection architectures determining various trade-offs between cost and performance. An automated methodology for optimizing FPGA-based MPSoC interconnect architectures is summarized in this poster paper. Based on the application communication requirements, the methodology concurrently defines the structure of the interconnect and the communication task scheduling, taking into account possible dependencies between tasks under given area constraints. The resulting architecture improves the level of communication parallelism while containing area and power costs.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132648278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Towards a guided design flow for heterogeneous reconfigurable architectures 面向异构可重构体系结构的引导设计流程
2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293991
T. Bostelmann, S. Sawitzki
{"title":"Towards a guided design flow for heterogeneous reconfigurable architectures","authors":"T. Bostelmann, S. Sawitzki","doi":"10.1109/FPL.2015.7293991","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293991","url":null,"abstract":"In this work we present a concept of an architecture design flow for heterogeneous reconfigurable architectures. We have a special focus on high flexibility regarding the architecture design. We cover architectures from fine-grained island-style FPGAs and heterogeneous hierarchical structures through to coarse-grained reconfigurable architectures (CGRAs). Our goal is to make the development and optimization of reconfigurable architectures more efficient and convenient. Therefore our design flow includes a graphical architecture editor, which allows the user to adapt the global design structure as well as the detailed implementation of the logic blocks. An analysis tool gives the user a statistical feedback about the resource utilization of the architecture under development for a given set of benchmark applications to allow a directed exploration and optimization. We describe the envisioned design flow and compare it to a manual design flow. Finally we present the parts of the toolset that are already operational and describe how we are planning to implement the remaining tools.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133289052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Parallel feature extraction and heterogeneous object-detection for multi-camera driver assistance systems 多摄像头驾驶辅助系统的并行特征提取与异构目标检测
2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293975
S. Wonneberger, Peter Mühlfellner, Pedro Ceriotti, T. Graf, Rolf Ernst
{"title":"Parallel feature extraction and heterogeneous object-detection for multi-camera driver assistance systems","authors":"S. Wonneberger, Peter Mühlfellner, Pedro Ceriotti, T. Graf, Rolf Ernst","doi":"10.1109/FPL.2015.7293975","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293975","url":null,"abstract":"We present a flexible architecture for image-based feature detection and object classification on an FPGA. This architecture is tailored to the requirements of future driver assistance systems, which will make it necessary to detect a wide range of different object types in multi-camera systems requiring highly efficient hardware. In contrast to other designs, which typically address a specific object type or only accelerate early processing steps, the proposed pipeline offers different operation modes to switch resources for either detection or classification speed. In addition, the architecture can incorporate heterogeneous processors for different feature types. The design is tailored to support any object detection system using weak features and cascaded classifiers. For evaluation, a classic Viola Jones Detector is implemented being fully compatible with OpenCV.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129873560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Efficient assembly for high order unstructured FEM meshes 高阶非结构化有限元网格的高效装配
2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1145/3024064
P. Burovskiy, Paul Grigoras, S. Sherwin, W. Luk
{"title":"Efficient assembly for high order unstructured FEM meshes","authors":"P. Burovskiy, Paul Grigoras, S. Sherwin, W. Luk","doi":"10.1145/3024064","DOIUrl":"https://doi.org/10.1145/3024064","url":null,"abstract":"The Finite Element Method (FEM) is a common numerical technique used for solving Partial Differential Equations (PDEs) on complex domain geometries. Large and unstructured FEM meshes are used to represent the computation domains which makes an efficient mapping of the Finite Element Method onto FPGAs particularly challenging. The focus of this paper is on assembly mapping, a key kernel of FEM, which induces the sparse and unstructured nature of the problem. We translate FEM vector assembly mapping into data access scheduling to perform vector assembly directly on the FPGA, as part of the hardware pipeline. We show how to efficiently partition the problem into dense and sparse sub-problems which map well onto FPGAs. The proposed approach, implemented on a single FPGA could outperform highly optimised FEM software running on two Xeon E5-2640 processors.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"401 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129222987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
OpenCL computing on FPGA using multiported OpenCL计算在FPGA上使用多端口
2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293983
Tahsin Turker Mutlugun, Sheng-de Wang
{"title":"OpenCL computing on FPGA using multiported","authors":"Tahsin Turker Mutlugun, Sheng-de Wang","doi":"10.1109/FPL.2015.7293983","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293983","url":null,"abstract":"This paper focuses on memory access improvements for the OpenCL architecture for FPGAs with the goal of achieving trade-off between performance and required resources. In OpenCL compute units, there is usually a linear relation between computation time and local memory access latency. This latency is normally hidden by increasing the parallel workload. However, with such an approach, the target FPGA device could easily run out of resources. In this work, conflict-free multiported memories are used to minimize local memory access latency. Experiments show that multiported memories can successfully increase computation speed and reduce the required parallel workload for maximum throughput to practical amounts.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116678709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Energy efficient partitioning of dynamic reconfigurable MRAM-FPGAs 动态可重构mram - fpga的节能分区
2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293947
A. Ahari, Mojtaba Ebrahimi, M. Tahoori
{"title":"Energy efficient partitioning of dynamic reconfigurable MRAM-FPGAs","authors":"A. Ahari, Mojtaba Ebrahimi, M. Tahoori","doi":"10.1109/FPL.2015.7293947","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293947","url":null,"abstract":"Emerging non-volatile Magnetic Random Access Memory (MRAM) is a promising alternative for replacement of SRAM-based configuration bits of conventional FPGAs. However, the costs of reconfiguration in MRAM-FPGAs are typically higher than SRAM-FPGAs due to the high write latency and energy of MRAM. In this paper, a novel energy-efficient partitioning technique is proposed to minimize the number of reconfigurations and content updates for dynamic reconfigurable MRAM-FPGAs. The simulation results show that the proposed technique significantly reduces the reconfiguration energy (up to 68.1% on average) as compared to the existing partitioning techniques.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128831762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
In-field vulnerability analysis of hardware-accelerated computer vision applications 硬件加速计算机视觉应用的现场漏洞分析
2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7294003
Ioannis Chadjiminas, C. Kyrkou, T. Theocharides, M. Michael, Christos Ttofis
{"title":"In-field vulnerability analysis of hardware-accelerated computer vision applications","authors":"Ioannis Chadjiminas, C. Kyrkou, T. Theocharides, M. Michael, Christos Ttofis","doi":"10.1109/FPL.2015.7294003","DOIUrl":"https://doi.org/10.1109/FPL.2015.7294003","url":null,"abstract":"In this paper, we propose an FPGA-based emulation framework that can provide dynamic vulnerability analysis for hardware-accelerated computer vision applications. The framework can be integrated alongside the targeted application, to allow for run-time, in-field, dynamically adjusted vulnerability analysis in real-world conditions, taking into consideration the non-deterministic parameters of the computer vision algorithm computations. We evaluate the proposed framework in real-time using an FPGA platform, for an obstacle avoidance (OA) computer vision application and its disparity estimation kernel to study the impact of Single-Event Upsets (SEUs).","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122991038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A scalable architecture for multi-class visual object detection 一个可扩展的多类视觉目标检测体系结构
2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293961
Siddharth Advani, Yasuki Tanabe, K. Irick, J. Sampson, N. Vijaykrishnan
{"title":"A scalable architecture for multi-class visual object detection","authors":"Siddharth Advani, Yasuki Tanabe, K. Irick, J. Sampson, N. Vijaykrishnan","doi":"10.1109/FPL.2015.7293961","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293961","url":null,"abstract":"As high-fidelity small form-factor cameras become increasingly available and affordable, there will be a subsequent growth and emergence of vision-based applications that take advantage of this increase in visual information. The key challenge is for the embedded systems, on which the bulk of these applications will be deployed, to maintain real-time performance in the midst of the exponential increase in spatial and temporal visual data. For example, a useful vision-based driver assistance system needs to locate and identify critical objects such as pedestrians, other vehicles, pot-holes, animals, and street signs with latency small enough to allow a human driver to react accordingly. In this work, we propose a digital accelerator architecture for a high-throughput, robust, scalable, and tunable visual object detection pipeline based on Histogram of Oriented Gradients (HOG) features. From a systems perspective, efficacy can be measured in terms of speed, accuracy, energy efficiency and scalability in performing such visual tasks. Since each application dictates the criticality of any one of these dimensions, our proposed architecture exposes design-time parameters that can take advantage of domain-specific knowledge while supporting tune-ability through run-time configurations. To evaluate the effectiveness of our vision accelerator we map the architecture to a modern FPGA and demonstrate full HD video processing at 30 fps (frames per second) operating at a conservative 100 MHz clock. Evaluations on a single object class show throughput improvements of 2× and 5× over GPU and multi-threaded CPU implementations respectively. Further more we provide a pathway for enhanced scalability for the many-class problem and achieve over 20× improvement over an equivalent CPU implementation for 5 object classes.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134405185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
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