2015 25th International Conference on Field Programmable Logic and Applications (FPL)最新文献_第6页

Automatic generation of high throughput energy efficient streaming architectures for arbitrary fixed permutations 为任意固定排列自动生成高吞吐量、高能效的流架构

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293944

Ren Chen, V. Prasanna

引用次数: 18

SysAlloc: A hardware manager for dynamic memory allocation in heterogeneous systems SysAlloc:异构系统中动态内存分配的硬件管理器

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293959

Zeping Xue, David B. Thomas

{"title":"SysAlloc: A hardware manager for dynamic memory allocation in heterogeneous systems","authors":"Zeping Xue, David B. Thomas","doi":"10.1109/FPL.2015.7293959","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293959","url":null,"abstract":"System-on-chip designs are increasingly complex and dynamic, with many IP cores, CPUs and off-chip Memories interconnected via shared buses. Static allocation of RAM resources requires designers to analyse the memory needs of each component, which can lead to poor memory efficiency, and is infeasible in a dynamically changing system. Dynamic memory allocation is one solution to this problem, but is usually only supported in software. We propose SysAlloc, a hardware-based dynamic memory allocation scheme for heterogeneous systems, which allows software and hardware to access a shared memory allocator, and allows dynamic memory allocation in the absence of software. Our allocation protocol is accessible to any client which can perform memory reads and writes over a shared bus, including software, RTL, and HLS clients, and can scale at run-time to any number of active clients. In contrast to existing designs, the proposed allocator can manage DDR-scale memories while having constant FPGA resource utilisation. We evaluate SysAlloc's protocol and memory manager in a Zynq system with both software and hardware clients, demonstrating scaling to 15 concurrent clients, and a peak system allocation rate of 1.36 million allocations/second when managing 128MB of DDR for 4 clients.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129067835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Towards efficient discrete Gaussian sampling for lattice-based cryptography 基于格的密码学的高效离散高斯采样

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293949

Chaohui Du, Guoqiang Bai

引用次数: 29

Enabling seamless execution on hybrid CPU/FPGA systems: Challenges & directions 在混合CPU/FPGA系统上实现无缝执行:挑战与方向

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7294022

Meena Belwal, M. Purnaprajna, Sudarshan TSB

{"title":"Enabling seamless execution on hybrid CPU/FPGA systems: Challenges & directions","authors":"Meena Belwal, M. Purnaprajna, Sudarshan TSB","doi":"10.1109/FPL.2015.7294022","DOIUrl":"https://doi.org/10.1109/FPL.2015.7294022","url":null,"abstract":"Today's computing systems are heterogeneous, with diverse micro-architectures. It is common to design systems comprising multi-core CPUs, Digital Signal Processors (DSP) and Graphic Processing Units (GPUs). In addition to these devices, the extensive configurability and parallelism in Field Programmable Gate Arrays (FPGAs) has proven to be advantageous for accelerating complex computational problems. In comparison to CPUs, DSPs and GPUs, FPGAs have a distinctly different microarchitecture. In this context, enabling seamless application execution in a system composed of FPGAs alongside CPUs, is a major challenge. As a consequence, simplifying programmability of hybrid CPU/FPGA systems demands innovations in system software support. There has been research in extending the traditional CPU-only system techniques to CPU/FPGA based hybrid systems to make way for FPGA-based mainstream computing. This article surveys techniques in dynamic task management aimed at reducing or completely eliminating the burden of operating system writers for CPU/FPGA hybrid systems and provide insight to researchers to explore further.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127096880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

FPGA-based all-digital software defined radio system demonstration 基于fpga的全数字软件无线电系统演示

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293970

R. Cordeiro, André Prata, Arnaldo S. R. Oliveira, N. Carvalho, J. Vieira

引用次数: 4

Recursive pipelined genetic propagation for bilevel optimisation 递归流水线遗传传播的双层优化

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7293943

Shengjia Shao, Liucheng Guo, Ce Guo, T. Chau, David B. Thomas, W. Luk, Stephen Weston

引用次数: 2

An LZ77-style bit-level compression for trace data compaction 用于跟踪数据压缩的lz77风格的位级压缩

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-08 DOI: 10.1109/FPL.2015.7294006

Kai-Uwe Irrgang, Thomas B. Preußer

引用次数: 6

Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices 面向ARM-FPGA混合器件的OpenCL工作组合成优化

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-07 DOI: 10.1109/FPL.2015.7294016

Mohammad Hosseinabady, J. Núñez-Yáñez

引用次数: 10

An automated technique to generate relocatable partial bitstreams for Xilinx FPGAs 为赛灵思fpga生成可重定位部分位流的自动化技术

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-07 DOI: 10.1109/FPL.2015.7293980

R. Oomen, T. D. A. Nguyen, Akash Kumar, H. Corporaal

{"title":"An automated technique to generate relocatable partial bitstreams for Xilinx FPGAs","authors":"R. Oomen, T. D. A. Nguyen, Akash Kumar, H. Corporaal","doi":"10.1109/FPL.2015.7293980","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293980","url":null,"abstract":"Partial reconfiguration is a technique used to increase the flexibility of an FPGA-based system by reprogramming parts of the system dynamically without interrupting the operation of the other modules. Despite the runtime benefits offered by partially reconfigurable (PR) systems, creating and storing partial bitstreams (PBs) are becoming major concerns for system architects when the numbers of reconfigurable partitions (RPs) and PR modules (PRMs) increase. It takes significant amount of time to generate the PBs for PR systems with large number of RPs and PRMs. More importantly, when the mapping relationship between PRMs and RPs is many-to-many, several almost-identical PBs of one PRM must be stored separately which leads to inefficient utilization of the memory storage. Therefore, bitstream relocation is drawing interests from the research community as a viable solution. Yet almost none of the works are able to demonstrate a coherent method to not only create relocatable PBs for complex and large PRMs in variable-size RPs but also how to do that automatically to free the designer from the tedious and error prone manual processes. In this paper, we propose a new technique to fill that gap. The method is successfully developed for Xilinx Virtex 7 devices using Vivado design tool flow.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126653956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Reduction calculator in an FPGA based switching Hub for high performance clusters 基于FPGA的高性能集群交换集线器中的缩减计算器

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-10-07 DOI: 10.1109/FPL.2015.7293985

Takuya Kuhara, Chiharu Tsuruta, T. Hanawa, H. Amano

引用次数: 10