2015 25th International Conference on Field Programmable Logic and Applications (FPL)最新文献_第7页

Mind the (synthesis) gap: Examining where academic FPGA tools lag behind industry 注意(合成)差距:检查FPGA工具落后于工业的地方

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-02 DOI: 10.1109/FPL.2015.7294007

Eddie Hung

引用次数: 15

Placing partially reconfigurable stream processing applications on FPGAs 将部分可重构的流处理应用程序放在fpga上

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-02 DOI: 10.1109/FPL.2015.7294001

Nicolae Bogdan Grigore, Dirk Koch

引用次数: 6

Optimizing energy efficient low-swing interconnect for sub-threshold FPGAs 优化亚阈值fpga的节能低摆幅互连

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7293979

He Qi, Oluseyi A. Ayorinde, Yu Huang, B. Calhoun

引用次数: 5

A framework for integrated monitoring of real-time embedded SoC 嵌入式SoC实时集成监控框架

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7293987

G. Valente

引用次数: 1

Estimating circuit delays in FPGAs after technology mapping 技术映射后fpga电路延迟估计

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7294010

Berg Severens, Elias Vansteenkiste, Karel Heyse, D. Stroobandt

{"title":"Estimating circuit delays in FPGAs after technology mapping","authors":"Berg Severens, Elias Vansteenkiste, Karel Heyse, D. Stroobandt","doi":"10.1109/FPL.2015.7294010","DOIUrl":"https://doi.org/10.1109/FPL.2015.7294010","url":null,"abstract":"An FPGA implementation requires a significant effort of the hardware designer, who optimizes FPGA designs by going through many time-consuming CAD flow iterations. These iterations provide two types of feedback: (1) the FPGA performance and (2) the identification of the parts having the highest impact on the FPGA performance. Both depend on the wirelength behavior. Studies have been dedicated to the estimation of local [5] and global [4] wirelengths, but to our knowledge both performance estimations and identification of the critical zone are not present in literature. Therefore this paper, firstly, presents a comparison of three performance estimation techniques: logic depth, Monte Carlo simulation and fast placement (ordered from low to high accuracy and runtime). Secondly, four methods identifying the critical zone are compared. Results show that Monte Carlo simulations provide a good identification of the parts having the highest impact on the performance. We conclude that Monte Carlo simulations provide useful feedback within a short runtime (about 30 times faster than placement), reducing the time-to-market of FPGA implementations.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131689516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

ParaLaR: A parallel FPGA router based on Lagrangian relaxation 基于拉格朗日松弛的并行FPGA路由器

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7294012

Chin Hau Hoo, Akash Kumar, Yajun Ha

引用次数: 21

Characterisation of feasibility regions in FPGAs under adaptive DVFS 自适应DVFS下fpga可行性区域的表征

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7293998

Nizar Dahir, Pedro B. Campos, G. Tempesti, M. Trefzer, A. Tyrrell

{"title":"Characterisation of feasibility regions in FPGAs under adaptive DVFS","authors":"Nizar Dahir, Pedro B. Campos, G. Tempesti, M. Trefzer, A. Tyrrell","doi":"10.1109/FPL.2015.7293998","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293998","url":null,"abstract":"Implementing Dynamic Voltage and Frequency Scaling (DVFS) is a non-trivial task on FPGAs and requires knowledge about the feasible voltage and frequency (VF) ranges as a first step. The VF feasible ranges depend not only on the size of the critical path in the design but also on the inter- and intra-die variability on the FPGA die. Moreover, the variations in the configuration of the FPGA highly affect feasible VF ranges. Therefore, it is crucial to characterise feasibility by studying the relationship between feasible VF regions and these sources of variability in FPGAs. In this paper we employ a self-checking multiplier which uses residue codes and DVFS implemented on the programmable logic component of a Xilinx Zynq ZC702 device as an error-detection circuit to study these feasible regions. Results show that, as expected, feasible VF ranges vary with FPGA configuration. More interestingly, significant variation of the feasible VF regions is found for different dies. These results highlight the necessity of dynamic self-testing as a part of an adaptive DVFS implementation on FPGAs. Employing the techniques presented in this work enables the implementation of efficient adaptive on-line DVFS on programmable logic while ensuring reliability.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"18 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116091579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow 可由Verilog-to-Routing (VTR) CAD流进行目标合成的FPGA结构

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7293955

Jin Hee Kim, J. Anderson

引用次数: 24

Static hardware task placement on multi-context FPGA using hybrid genetic algorithm 基于混合遗传算法的多上下文FPGA静态硬件任务配置

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7293954

Hao Liang, Sharad Sinha, Rakesh Warrier, Wei Zhang

{"title":"Static hardware task placement on multi-context FPGA using hybrid genetic algorithm","authors":"Hao Liang, Sharad Sinha, Rakesh Warrier, Wei Zhang","doi":"10.1109/FPL.2015.7293954","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293954","url":null,"abstract":"Field Programmable Gate Arrays (FPGAs) are becoming pervasive in various kinds of computationally demanding applications. Working in a tightly coupled processor-coprocessor architecture, FPGAs are often anticipated to accelerate multiple fine-grained or coarse-grained tasks simultaneously. Single-context FPGAs are commonly used in such systems. With the recent development of emerging memory technologies, multi-context FPGAs that support dynamic reconfiguration with high-density non-volatile memories become feasible. Compared to single-context FPGAs, multi-context FPGAs are able to accelerate significantly more tasks with only moderate area and power overhead. However, the best way to utilize the computation capacity advantage of multi-context FPGAs for hardware task mapping remains an interesting and unexploited problem. In this paper, we first propose the framework of a processor-coprocessor architecture with multi-context FPGA as the coprocessor for multiple-task acceleration. Under the framework, a hybrid placement strategy based on genetic and greedy algorithms is proposed to efficiently place a set of tasks onto the multi-context FPGA to achieve the best logic capacity utilization. Experiments on real and synthetic benchmarks demonstrate the efficiency of the proposed algorithm compared with other general approaches.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123128192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

CoRAM++: Supporting data-structure-specific memory interfaces for FPGA computing CoRAM++:支持用于FPGA计算的特定于数据结构的内存接口

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7294017

G. Weisz, J. Hoe

引用次数: 22