2015 25th International Conference on Field Programmable Logic and Applications (FPL)最新文献_第8页

Fine-tuning CLB placement to speed up reconfigurations in NVM-based FPGAs 微调CLB位置以加快基于nvm的fpga的重新配置

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7294013

Yuan Xue, P. Cronin, Chengmo Yang, J. Hu

{"title":"Fine-tuning CLB placement to speed up reconfigurations in NVM-based FPGAs","authors":"Yuan Xue, P. Cronin, Chengmo Yang, J. Hu","doi":"10.1109/FPL.2015.7294013","DOIUrl":"https://doi.org/10.1109/FPL.2015.7294013","url":null,"abstract":"Non-volatile memories (NVMs) outperform traditional SRAMs in terms of low power consumption, high capacity, near-zero power-on delay, and high error-resistance. Researchers have demonstrated the possibilities of implementing FPGA building blocks with various types of NVMs. However, NVMs also bring several new design challenges to FPGAs: the slow write performance of NVM may degrade FPGA (re)configuration speed, while the limited write endurance of NVM constrains the number of times that the FPGA can be (re)configured. Unfortunately, none of these NVM features are taken into consideration in current FPGA synthesis tools, which have been optimized solely for SRAM-based FPGAs. To tackle this limitation, we propose to make the FPGA placement process aware of the slow and costly NVM writes. Our contributions are three-fold: We first construct mathematical models to characterize reconfiguration costs in NVM-based FPGAs. Second, we identify three types of flexibilities that can be exploited to reduce the reconfiguration cost. Finally, we present three approaches for designers to fine-tune the placement process to balance the reconfiguration cost and traditional timing and routability constraints according to their needs. The proposed algorithms are incorporated in Verilog-to-Routing (VTR) CAD tool. Experiments on standard MCNC benchmark circuits show that our approach eliminates up to 67% NVM writes during the reconfiguration process, thus effectively improving the performance and endurance of NVM-based FPGAs.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133500125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Serial and parallel interleaved modular multipliers on FPGA platform FPGA平台上的串行和并行交错模块化乘法器

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7293986

Khalid Javeed, Xiaojun Wang, Mike Scott

{"title":"Serial and parallel interleaved modular multipliers on FPGA platform","authors":"Khalid Javeed, Xiaojun Wang, Mike Scott","doi":"10.1109/FPL.2015.7293986","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293986","url":null,"abstract":"Modular multiplication is a core operation in all public key based cryptosystems. The performance of these cryptosystems can be enhanced substantially by incorporating an optimized modular multiplier. This paper presents serial and parallel radix-4 modular multipliers based on interleaved multiplication algorithm and Montgomery power laddering technique. A serial radix-4 interleaved modular multiplier provides 50% reduction in the required clock cycles. In addition to the reduction in clock cycles, a parallel modular multiplier maintains a critical path delay comparable to the bit serial interleaved multipliers. The proposed designs are implemented in Verilog HDL and synthesized targeting virtex-6 FPGA platform using Xilinx ISE 14.2 Design suite. The serial radix-4 multiplier computes a 256-bit modular multiplication in 1.3μs, occupies 3.9K LUTs, and runs at 96 MHz. The parallel radix-4 multiplier takes 0.77μs, occupies 5.3K LUTs, and runs at 166 MHz. The results show that the parallel radix-4 modular multiplier provides 62% and 49% speed-up over the corresponding bit serial and bit parallel versions, respectively. Thus, these designs are suitable to accelerate modular multiplication in many cryptographic processors.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121758528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 41

Over effective hard real-time hardware tasks scheduling and allocation 有效的硬件实时任务调度和分配

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7293994

Zakarya Guettatfi, O. Kermia, A. Khouas

{"title":"Over effective hard real-time hardware tasks scheduling and allocation","authors":"Zakarya Guettatfi, O. Kermia, A. Khouas","doi":"10.1109/FPL.2015.7293994","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293994","url":null,"abstract":"Hardware task scheduling and allocation at runtime increase the chip utilization ration and improve the system performance by exploring partially reconfigurable Field-Programmable Gate Arrays (FPGAs). Partial reconfiguration enables to change all or parts of the system hardware during the execution, in order to gain efficiency over static system. Hardware-software real-time operating systems (RTOS) are often used to develop applications for embedded systems with complex time and resource constraints. In hard real-time systems, failure to meet its time constraints may lead to disastrous consequences. However, reconfigurable systems still lack an OS foundation that covers both software and hardware tasks dor hard real-time requirements. The objective of this work is to formalize an abstraction layer combining safety-critical RTOS, like SafeRTOS, μC/OS-II or Xenomai. on the one hand. On the other hand, we give some leads on hardware tasks scheduling and allocation effective algorithms in order to manage a hard real time software-hardware configuration. This paper presents, succinctly, a preliminary work which can allow the utilization of a safety-critical RTOS for managing software tasks, while hardware tasks are relocatabled and multi-shaped through GoAhead.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121476997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A rapid prototyping framework for nano-photonic accelerators 纳米光子加速器的快速原型设计框架

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7294004

Wolfgang Büter, A. Ortiz, A. Ali, S. Mahmood, S. Arefin, V. P. Sreenivas, R. B. Bergman

引用次数: 0

Inter-procedural resource sharing in High Level Synthesis through function proxies 通过功能代理实现高级综合中的程序间资源共享

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7293958

Marco Minutoli, Vito Giovanni Castellana, Antonino Tumeo, Fabrizio Ferrandi

{"title":"Inter-procedural resource sharing in High Level Synthesis through function proxies","authors":"Marco Minutoli, Vito Giovanni Castellana, Antonino Tumeo, Fabrizio Ferrandi","doi":"10.1109/FPL.2015.7293958","DOIUrl":"https://doi.org/10.1109/FPL.2015.7293958","url":null,"abstract":"Modular design is becoming increasingly important in High Level Synthesis (HLS) flows. Current HLS flows generate hierarchical and modular designs that mimic the structure and call graph of the input specification by translating functions into modules. Function calls are translated by instantiating the callee module in the data-path of its caller, allowing for resource sharing when the same function is called multiple times. However, if two different callers invoke the same function, current HLS flows cannot share the instance of the module between the two callers, even if they invoke the function in a mutually exclusive way. In this paper, we propose a methodology that enables sharing of (sub)modules across modules boundaries. Sharing is obtained through function proxies, which act as forwarders of function calls in the original specification to shared modules without reducing performance. Building on the concept of function proxies, we propose a methodology and the related components to perform HLS of function calls through function pointers, without requiring complete static knowledge of the alias set (point-to set). We show that module sharing through function proxies provides valuable area savings and no significant impacts on the execution delays, and that our synthesis approach for function pointers enables dynamic polymorphism.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124624515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

FPGA based nonlinear Support Vector Machine training using an ensemble learning 基于FPGA的非线性支持向量机集成学习训练

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7293972

Mudhar Bin Rabieah, C. Bouganis

引用次数: 21

Hybrid FPGA debug approach FPGA混合调试方法

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7294023

Zdravko Panjkov, A. Wasserbauer, T. Ostermann, R. Hagelauer

引用次数: 7

A scalable FPGA architecture for nonnegative least squares problems 非负最小二乘问题的可扩展FPGA架构

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7293750

Alric Althoff, R. Kastner

引用次数: 3

PushPush: Seamless integration of hardware and software objects via function calls over AXI PushPush:通过AXI上的函数调用无缝集成硬件和软件对象

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7294024

Shane T. Fleming, I. Beretta, David B. Thomas, G. Constantinides, D. Ghica

{"title":"PushPush: Seamless integration of hardware and software objects via function calls over AXI","authors":"Shane T. Fleming, I. Beretta, David B. Thomas, G. Constantinides, D. Ghica","doi":"10.1109/FPL.2015.7294024","DOIUrl":"https://doi.org/10.1109/FPL.2015.7294024","url":null,"abstract":"FPGA systems are moving towards a system-on-chip model, both at the architectural level and in the development tools. Developers are able to design and implement IP using a mixture of HLS, RTL, and software, then integrate them with third-party IP cores and hardened CPUs using one or more shared memory buses. This allows functionality to be easily connected together at the bus level, but accessing IP core functionality requires designers to support each component's protocol and co-ordinate hardware from a CPU. This paper presents a protocol called PushPush, which allows HLS, RTL, and software components to expose functionality as strongly typed functions, and allows any component to access functions exposed by any other component in the system. The protocol is designed for maximum efficiency in memory buses such as AXI and Avalon, reducing each function call to two burst writes delivering both data and control, minimising bus traffic and eliminating the need for global polling or interrupt delivery. We demonstrate this approach in a Zynq environment, using components written in C++ (ARM/Linux), C (Microblaze), Vivado HLS (Logic), and Verity (Logic). We show that any component can call functions exposed by any other component, without knowing where or how that function is located. Performance is at least 1 million function calls/sec between any pair of components, and rises to 4 million function calls/sec between pairs of Vivado HLS components.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124121537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Automatic support for multi-module parallelism from computational patterns 自动支持来自计算模式的多模块并行

2015 25th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2015-09-01 DOI: 10.1109/FPL.2015.7294011

N. George, HyoukJoong Lee, D. Novo, Muhsen Owaida, D. Andrews, K. Olukotun, P. Ienne

{"title":"Automatic support for multi-module parallelism from computational patterns","authors":"N. George, HyoukJoong Lee, D. Novo, Muhsen Owaida, D. Andrews, K. Olukotun, P. Ienne","doi":"10.1109/FPL.2015.7294011","DOIUrl":"https://doi.org/10.1109/FPL.2015.7294011","url":null,"abstract":"Field Programmable Gate Arrays (FPGAs) can be customized into application-specific architectures to achieve high performance and energy-efficiency. Unfortunately, they are yet to gain significant adoption by application developers due to their low-level programming model. Moreover, to obtain good performance in an FPGA design, one often needs to correctly parallelize computation and balance the computational throughput with the available data access bandwidth. To address the programming model problem, recent efforts have focused on composing applications out of parallel computational patterns, such as map, reduce, zipWith and foreach, and leveraging the properties of these patterns to generate highly parallel hardware modules capable of high performance. In this work, we focus on the problem of further improving the performance and show that we can utilize the knowledge of how data is consumed and produced by these computational patterns in conjunction with the information of the system architecture to automatically parallelize computations across multiple hardware modules. To achieve this, we automatically infer synchronization needs arising due to parallelization and generate a complete system that can obtain high performance for a given application. We evaluate our approach using seven applications from different domains and show that our automatically generated designs achieve performance improvements ranging from 1.8 to 9.4 times.","PeriodicalId":261014,"journal":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125968953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9