High speed ECC implementation on FPGA over GF(2m)

Abstract

High speed Elliptic Curve Cryptography (ECC) implementations on Field Programmable Gate Array (FPGA) are highly desirable for applications requiring high speed cost effective and flexible implementations of public key cryptography. Recently, many binary ECC hardware accelerators have been presented based on the Montgomery point multiplication by exploiting the underlying parallelism of the point multiplication (PM). In this paper, we present a combined Montgomery point multiplication algorithm to achieve low latency ECC point multiplication by using novel pipelined full precision parallel multipliers over GF(2m). We adopt a careful schedule of point operations to achieve low latency and a smart pipelining in the ECC architecture to reduce the critical path delay. Our proposed ECC architecture is implemented on Virtex5 (XCV5LX110) for a fair comparison and on Virtex7 (XC7VX550T) to quantify performance. Our Virtex5 based implementation over GF(2163), consumes 10363 slices, takes only 5.1 μs for an ECC point multiplication with a frequency of 153 MHz, and has a latency of 780 clock cycles. Our Virtex-5 performance outperforms the fastest reported work on the same platform. Our Virtex7 implementation which can compute an ECC PM in 3.50 μs at a frequency of 223 MHz while utilising only 8736 slices is the highest speed implementation reported to date on FPGA.