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2008 International Conference on Simulation of Semiconductor Processes and Devices最新文献

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Level shifts and gate interfaces as vital ingredients in modeling of charge trapping 电平移位和栅极界面是电荷捕获建模的重要组成部分
2008 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2008-10-10 DOI: 10.1109/SISPAD.2008.4648239
W. Goes, M. Karner, S. Tyaginov, P. Hehenberger, T. Grasser
{"title":"Level shifts and gate interfaces as vital ingredients in modeling of charge trapping","authors":"W. Goes, M. Karner, S. Tyaginov, P. Hehenberger, T. Grasser","doi":"10.1109/SISPAD.2008.4648239","DOIUrl":"https://doi.org/10.1109/SISPAD.2008.4648239","url":null,"abstract":"We present a detailed modeling study of charging and discharging traps in dielectrics used in modern semiconductor devices. Existing descriptions of charge trapping are often restricted to charge injection from the substrate and ignore the presence of the gate contact as a source/sink of charge carriers. This assumption loses its justification when the gate dielectric shrinks into the nanometer range. Furthermore, a novel picture of tunneling into and out of defects has emerged from first principles calculations which questions the conventional concept of fixed trap levels irrespective of their charge state. Consequently, focus is put on the development of a novel rigorous model merging both effects into one general description of charge trapping.","PeriodicalId":260253,"journal":{"name":"2008 International Conference on Simulation of Semiconductor Processes and Devices","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126502006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Atomistic modeling of dopant diffusion and segregation in strained SiGeC 应变SiGeC中掺杂物扩散和偏析的原子模型
2008 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2008-10-10 DOI: 10.1109/SISPAD.2008.4648305
S. Dunham, Hsiu-Wu Guo, Jakyoung Song, C. Ahn
{"title":"Atomistic modeling of dopant diffusion and segregation in strained SiGeC","authors":"S. Dunham, Hsiu-Wu Guo, Jakyoung Song, C. Ahn","doi":"10.1109/SISPAD.2008.4648305","DOIUrl":"https://doi.org/10.1109/SISPAD.2008.4648305","url":null,"abstract":"In this work, density functional theory calculations are used to calculate the separate effects of stress/strain and chemical binding on diffusion, segregation and solubility of dopants in group IV alloy materials. Kinetic lattice Monte Carlo calculations are used to extract the effects of anisotropic stress and random alloy distributions. We find that segregation and solubility is dominated by stress effects, but that chemical interactions of Ge and C with point defects have a significant effect on diffusivity in SiGeC alloys.","PeriodicalId":260253,"journal":{"name":"2008 International Conference on Simulation of Semiconductor Processes and Devices","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133108459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A surface potential model for bulk MOSFET which accurately reflects channel doping profile expelling fitting parameters 基于拟合参数的体MOSFET表面电位模型能准确反映沟道掺杂分布
2008 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2008-10-10 DOI: 10.1109/SISPAD.2008.4648290
H. Sakamoto, K. Watanabe, H. Arimoto, M. Tanizawa, S. Kumashiro
{"title":"A surface potential model for bulk MOSFET which accurately reflects channel doping profile expelling fitting parameters","authors":"H. Sakamoto, K. Watanabe, H. Arimoto, M. Tanizawa, S. Kumashiro","doi":"10.1109/SISPAD.2008.4648290","DOIUrl":"https://doi.org/10.1109/SISPAD.2008.4648290","url":null,"abstract":"A surface potential model for bulk MOSFET which accurately reflects channel doping profile is proposed. Only physical parameters such as device structures and doping profiles are used in the proposed model. For the vertical direction to channel, the model consistently integrates both surface potential and arbitral channel doping profiles in Poisson equation by using HiSIM2 framework. For channel direction, the model improves Pangpsilas quasi-2D Gaussian box model by taking the effect of source/drain junction depth into account. To accurately reflect the effect of the doping profile, drain current is evaluated by numerical integration using the calculated surface potential. The dependence of both short channel effect (SCE) and the reverse short channel effect (RSCE) on Vds, Vbs, channel length, junction depth and channel doping profiles, are expressed accurately without using any fitting parameters.","PeriodicalId":260253,"journal":{"name":"2008 International Conference on Simulation of Semiconductor Processes and Devices","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122469263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Micro magnetic simulation of write error probability in STT-MRAM STT-MRAM写入错误概率的微磁仿真
2008 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2008-10-10 DOI: 10.1109/SISPAD.2008.4648235
K. Kawabata, M. Tanizawa, K. Ishikawa, Y. Inoue
{"title":"Micro magnetic simulation of write error probability in STT-MRAM","authors":"K. Kawabata, M. Tanizawa, K. Ishikawa, Y. Inoue","doi":"10.1109/SISPAD.2008.4648235","DOIUrl":"https://doi.org/10.1109/SISPAD.2008.4648235","url":null,"abstract":"STT MRAM is one of the most promising candidates for the next generation non-volatile memory. The STT-MRAM write operation is to switch the magnetization direction of ferromagnetic free layer with spin transfer torque by current injection. A ferromagnetic thin film used in it is so small volume that the thermal fluctuation due to ambient temperature has to be considered in the device design. Its process is described by a stochastic probability distribution. In this paper, a write error probability function in STT MRAM at finite temperature is investigated based on the result of LLG micro magnetic simulation. The function is found to be a Weibull type function with modulus, beta. The physical meanings of beta is found to be an index of competitions between thermal activation process and spin transfer torque ones in switching of STT MRAM at finite temperature.","PeriodicalId":260253,"journal":{"name":"2008 International Conference on Simulation of Semiconductor Processes and Devices","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123970670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Modulated exchange and gate oxide thickness effects on surface roughness limited mobility 调制交换和栅极氧化物厚度对表面粗糙度的影响限制了迁移率
2008 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2008-10-10 DOI: 10.1109/SISPAD.2008.4648298
S. Wakahara
{"title":"Modulated exchange and gate oxide thickness effects on surface roughness limited mobility","authors":"S. Wakahara","doi":"10.1109/SISPAD.2008.4648298","DOIUrl":"https://doi.org/10.1109/SISPAD.2008.4648298","url":null,"abstract":"Many-body effects are modulated by the roughness of the Si-SiO2 interface of MOSFET, and act like scattering potentials. The theory of surface roughness scattering has considered only the modulation of the Hartree potential. We reformulate the theory to incorporate many-body effects, and show that exchange decreases mobility about 35% with thick gate oxide. We also calculate the dependence of mobility on the oxide thickness. This dependence is influenced by exchange significantly.","PeriodicalId":260253,"journal":{"name":"2008 International Conference on Simulation of Semiconductor Processes and Devices","volume":"238 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121216102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Emission efficiency dependence on the tilted angle of nanogaps in surface conduction electron-emitter 表面导电电子发射极中纳米间隙倾角对发射效率的影响
2008 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2008-10-10 DOI: 10.1109/SISPAD.2008.4648273
Yiming Li, Yi-Ting Kuo, Hui-Wen Cheng, Ta-Ching Yeh, Hsiang‐Yu Lo, Mei-Tsao Chiang, C. Mo
{"title":"Emission efficiency dependence on the tilted angle of nanogaps in surface conduction electron-emitter","authors":"Yiming Li, Yi-Ting Kuo, Hui-Wen Cheng, Ta-Ching Yeh, Hsiang‐Yu Lo, Mei-Tsao Chiang, C. Mo","doi":"10.1109/SISPAD.2008.4648273","DOIUrl":"https://doi.org/10.1109/SISPAD.2008.4648273","url":null,"abstract":"In this work, the emission efficiency of the novel surface conduction electron-emitter corresponding to tilted angles (thetas) of the driving electrode is studied numerically. Due to the small angle, the emitter apex becomes significant and induces large electric field. The large electric field then attracts more particles into vacuum and then increases the emission current. However, the structure of the driving electrode limits the electron trajectory while the angle decreases, and it reflects the portion of collected current by the anode decreases and makes a drop in emission efficiency. It shows there is the highest emission efficiency (about 37%) under an optimum angle thetas = 60deg. The result provides an insight into the relation between emission efficiency and emitter apex.","PeriodicalId":260253,"journal":{"name":"2008 International Conference on Simulation of Semiconductor Processes and Devices","volume":"421 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115578290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Device scaling of high performance MOSFET with metal gate high-k at 32nm technology node and beyond 金属栅极高k的高性能MOSFET在32nm及以上技术节点的器件缩放
2008 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2008-10-10 DOI: 10.1109/SISPAD.2008.4648299
Xinlin Wang, G. Shahidi, P. Oldiges, M. Khare
{"title":"Device scaling of high performance MOSFET with metal gate high-k at 32nm technology node and beyond","authors":"Xinlin Wang, G. Shahidi, P. Oldiges, M. Khare","doi":"10.1109/SISPAD.2008.4648299","DOIUrl":"https://doi.org/10.1109/SISPAD.2008.4648299","url":null,"abstract":"In this work, two different methodologies are used to quantitatively evaluate devices with metal high-k gate dielectrics for their scaling benefits over conventional polysilicon gate devices. For each method, device characteristics and ring oscillator delay calculations are performed. Our results show that aggressive channel length scaling continually provides transistor performance gain with the use of metal gate high-k technology. A band edge work function for the metal gate offers potential benefits for device scaling over conventional polysilicon gates for high performance (HP) application at the 32 nm CMOS technology node and beyond.","PeriodicalId":260253,"journal":{"name":"2008 International Conference on Simulation of Semiconductor Processes and Devices","volume":"302 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115219996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
2D/3D NEGF modeling of the impact of random dopants /dopant aggregation in silicon nano-transistors 硅纳米晶体管中随机掺杂物/掺杂物聚集影响的二维/三维NEGF模型
2008 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2008-10-10 DOI: 10.1109/SISPAD.2008.4648306
John R. Barker
{"title":"2D/3D NEGF modeling of the impact of random dopants /dopant aggregation in silicon nano-transistors","authors":"John R. Barker","doi":"10.1109/SISPAD.2008.4648306","DOIUrl":"https://doi.org/10.1109/SISPAD.2008.4648306","url":null,"abstract":"The discrete nature of dopants becomes apparent in nano-scaled devices leading to microvariability problems which cause large fluctuations in the performance of macroscopically identical devices. Since self-averaging fails, the approach reviewed here utilises self-consistent non-equilibrium Green function modelling to evaluate the effects of discrete random dopants in source and drain non-perturbatively.","PeriodicalId":260253,"journal":{"name":"2008 International Conference on Simulation of Semiconductor Processes and Devices","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126971689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Transient device simulation of trap-assisted leakage in non-volatile memory cell 非易失性存储单元中陷阱辅助泄漏的瞬态器件模拟
2008 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2008-10-10 DOI: 10.1109/SISPAD.2008.4648233
H. Watanabe
{"title":"Transient device simulation of trap-assisted leakage in non-volatile memory cell","authors":"H. Watanabe","doi":"10.1109/SISPAD.2008.4648233","DOIUrl":"https://doi.org/10.1109/SISPAD.2008.4648233","url":null,"abstract":"In order to study how a local trap degrades data retention characteristics of floating gate nonvolatile memory cell, a general-purpose Single-Electron Device Simulator (SEDS) developed for Si-dot is improved to carry out a very wide range transient analysis from 0.1 pico-seconds to 10 years. As a result, it is found that the data retention is degraded by the direct tunneling enhanced due to positive charge stored at the trap inside the inter-poly dielectric but not by trap-assisted tunneling.","PeriodicalId":260253,"journal":{"name":"2008 International Conference on Simulation of Semiconductor Processes and Devices","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127077261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Numerical modeling and design of single photon counter 4H-SiC avalanche photodiodes 单光子计数器4H-SiC雪崩光电二极管的数值模拟与设计
2008 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2008-10-10 DOI: 10.1109/SISPAD.2008.4648272
A. Akturk, N. Goldsman, S. Aslam, J. Sigwarth, F. Herrero
{"title":"Numerical modeling and design of single photon counter 4H-SiC avalanche photodiodes","authors":"A. Akturk, N. Goldsman, S. Aslam, J. Sigwarth, F. Herrero","doi":"10.1109/SISPAD.2008.4648272","DOIUrl":"https://doi.org/10.1109/SISPAD.2008.4648272","url":null,"abstract":"We report device performance investigation of 4H-SiC avalanche photodiodes (APDs) with or without absorbing AlGaN cap layers, as 4H-SiCspsila potential use in single photon counter APDs have drawn interest. Wide bandgap 4H-SiC photodiodes have low dark current levels at high temperatures and under intense radiation compared to silicon, and the 4H-SiC APDs are ldquosolar blindrdquo - transparent to the sunpsilas visible spectrum. Additionally, they offer avalanche multiplications approaching a million, making single photon count possible. However, design and optimization of single photon counter APDs require a thorough understanding of impact ionization and optical absorption at the material level, and steady-state and transient APD operation at the device level. Here we address both of these levels.","PeriodicalId":260253,"journal":{"name":"2008 International Conference on Simulation of Semiconductor Processes and Devices","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123228346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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