2023 IEEE Space Computing Conference (SCC)最新文献

{"title":"Performance modeling of a heterogeneous computing system based on the UCIe Interconnect Architecture","authors":"Tom Jose, D. Shankar","doi":"10.1109/SCC57168.2023.00009","DOIUrl":"https://doi.org/10.1109/SCC57168.2023.00009","url":null,"abstract":"In a heterogeneous computing environment, there exist a variety of computational units such as multicore CPUs, GPUs, DSPs, FPGAs, Analog modules, and ASICs. IP Vendors, Engineers, and Scientists working with heterogeneous computing systems face numerous challenges, including integration of IP Cores and components from different vendors, system reliability, hardware-software partitioning, task mapping, the interaction between compute and Memory, and reliable communication.For advanced designs, the industry typically develops a system-on-a-chip (SoC), where different functions are shrunk at each node and pack them onto a monolithic die. But this approach is becoming more complex and expensive at each node. Another way to develop a system-level design is to assemble complex dies in an advanced package. Chiplets are a way of modularizing that approach. Chiplets can be combined with other chiplets on an interposer in a single package. This provides several advantages over a traditional system on chip (SoC) or integrated board, in terms of reusable IP, heterogeneous integration, and verifying die functional behavior.In our work, a system-level model composed of chiplets-IO Chiplet, Low Power Core Chiplet, High-Performance Core Chiplet, audio video Chiplet, and Analog chiplet, are interconnected using Universal Chiplet Interconnect Express (UCIe) standard. We looked at different scenarios and configurations including advanced and standard packages, different traffic profiles, sizing of resources, and Retimer to extend the reach and evaluate events on timeout. We were able to identify the strengths and weaknesses of UCIe interconnect in the scope of mission applications and obtain the optimal configuration for each of the subsystems to meet the performance, power, and functional requirements.","PeriodicalId":258620,"journal":{"name":"2023 IEEE Space Computing Conference (SCC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124520011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"HPC in a Vacuum: Evaluating Future Space Microprocessors","authors":"Théa-Martine Gauthier","doi":"10.1109/scc57168.2023.00024","DOIUrl":"https://doi.org/10.1109/scc57168.2023.00024","url":null,"abstract":"Advanced algorithms dictated by future mission needs are pushing space-borne computing requirements. Current platforms used in manned and unmanned spaceflight are limited by the intersection of radiation tolerance, power consumption, computing performance and safety critical features. Until recently, advanced instruction set architectures (ISAs), algorithm specific instructions, high speed external interfaces and high performance on-chip networks were eschewed from processor designs and current production spacecraft processors are based on past computing paradigms.Advances in processor manufacturing, emerging ISAs and machine learning techniques will significantly impact future system-on-chip (SoC) designs, enabling true high-performance space computing. To better understand the computational requirements of modern spacecraft, a comprehensive set of benchmarks that include basic system characterization, high performance computing, navigation and landing, image recognition, route finding, data mining and machine learning are necessary to characterize candidate architectures. The analysis of these space flight focused algorithms will drive the design of next generation space computing SoCs.","PeriodicalId":258620,"journal":{"name":"2023 IEEE Space Computing Conference (SCC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124099844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ScOSA on the Way to Orbit: Reconfigurable High-Performance Computing for Spacecraft","authors":"D. Lüdtke, T. Firchau, Carlos Gonzalez Cortes, Andreas Lund, A. M. Nepal, Mahmoud M. Elbarrawy, Zain Alabedin Haj Hammadeh, Jan-Gerd Mess, Patrick Kenny, Fiona Brömer, Michael Mirzaagha, George Saleip, Hannah Kirstein, Christoph Kirchhefer, A. Gerndt","doi":"10.1109/SCC57168.2023.00015","DOIUrl":"https://doi.org/10.1109/SCC57168.2023.00015","url":null,"abstract":"The German Aerospace Center (DLR) is developing ScOSA (Scalable On-board Computing for Space Avionics) as a distributed on-board computing architecture for future space missions. The ScOSA architecture consists of commercial off-the-shelf (COTS) and radiation-tolerant nodes interconnected by a SpaceWire network. The system software provides services to enable parallel computing and system reconfiguration. This allows ScOSA to adapt to node errors and failures that COTS hardware is susceptible to in the space environment. In the ongoing ScOSA Flight Experiment project, a ScOSA system consisting of eight Xilinx Zynq systems-on-chip with dual-core ARM-based processors and a LEON3 radiation-tolerant processor is being built for launch on DLR’s next CubeSat in late 2024. In this flight experiment, not only all 18 cores but also the programmable logic will be used for high performance on-board data processing. This paper presents the current hardware and software architecture of ScOSA. The scalability of ScOSA is highlighted from both hardware and software perspectives. We present benchmark results of the ScOSA system and experiments of the ScOSA system software on ESA’s OPS-SAT in orbit in combination with a machine learning application for image classification.","PeriodicalId":258620,"journal":{"name":"2023 IEEE Space Computing Conference (SCC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129212628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The ring-buffer ROS2 executor: a novel approach for real-time ROS2 Space applications","authors":"Pablo Ghiglino, Guillermo Sarabia","doi":"10.1109/SCC57168.2023.00021","DOIUrl":"https://doi.org/10.1109/SCC57168.2023.00021","url":null,"abstract":"ROS2 (Robot Operating System Version 2) is an open-source software framework and suite of libraries that facilitates robotics application development and multi-core processing. ROS2 is becoming the de-facto standard for autonomous robotics application and recently. On the other hand, with the support of NASA and Blue Origin, Space-ROS -a Space applications specialized implementation of ROS2- is also starting to be used for Space autonomous applications, like landers and space robotics. ROS was designed to simplified and reduce the development time and effort required to write robotics applications and ROS2 kept this focus plus the main goal of enabling real-time robotics. In the initial design of ROS2, processing performance was given low priority, and, while an effort has been made to increase processing performance, it is not uncommon to face long latency in receiving sensor data or even non-negligible data losses. The research presented here shows a ROS2 executor implemented based on a lock-free ring-buffer that can not only increase by significantly the data processing rate with respect to the built-in ROS2 executors, but also reduce the processing consumption substantially. Successful performance results of this novel ring-buffer ROS2 executor are presented here and validated in several Space computers and the de-facto real-time benchmarking standard: the Raspberry Pi4 with Real-time Linux as operating system.","PeriodicalId":258620,"journal":{"name":"2023 IEEE Space Computing Conference (SCC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129215016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Battery Management System for On-Board Data-Driven State of Health Estimation for Aviation and Space Applications","authors":"Steffen Bockrath, J. Wachtler, M. Wenger, R. Schwarz, M. Pruckner, Vincent R. H. Lorentz","doi":"10.1109/SCC57168.2023.00023","DOIUrl":"https://doi.org/10.1109/SCC57168.2023.00023","url":null,"abstract":"To ensure a safe and economically valuable operation of a battery system over the whole lifetime, a battery management system is used for measuring and monitoring battery parameters and controlling the battery system. Since the battery performance decreases over its lifetime, a precise on-board aging estimation is needed to identify significant capacity degradation endangering the functionality and safety of a battery system. Especially for aviation and space applications, this can result in catastrophic scenarios. Therefore, in this work, a generic battery management system approach is presented considering aerospace application requirements. The modular hardware and software architecture and its components are described. Moreover, it is shown that the developed battery management system supports the execution of data-driven state of health estimation algorithms. For this purpose, aging estimation models are developed that only receive eight high-level parameters of partial charging profiles as input without executing further feature extraction steps and can thus be easily provided by a battery management system. Three different neural network architectures are implemented and evaluated: a fully connected neural network, a 1D convolutional neural network and a long short-term memory network. It is shown that all three aging models provide a precise state of health estimation by only using the obtained high-level parameters. The achieved fully connected neural network provides the best tradeoff between required memory resources and accuracy with an overall mean absolute percentage error of 0.41%.","PeriodicalId":258620,"journal":{"name":"2023 IEEE Space Computing Conference (SCC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122319829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"System Model Evaluation of RISC-V Cores for improved performance and fault tolerance","authors":"Tom Jose, D. Shankar","doi":"10.1109/SCC57168.2023.00022","DOIUrl":"https://doi.org/10.1109/SCC57168.2023.00022","url":null,"abstract":"As aerospace and defense firms are working towards developing future air and space platforms, decisions involving which hardware and software elements to use in their design need to be made. One significant design choice is the underlying Instruction Set Architecture (ISA) that defines the interface between the software and hardware for a processor. A relatively new ISA called RISC-V has emerged as an open-source alternative to commercial ISAs. Verifiable security, frozen base specification for long-term stability, designed for extensibility, and no license fee for modifications make RISC-V particularly well suited for aerospace and defense applications. It is important for the architect to evaluate not only the RISC-V core but the interaction of the core with other subsystems, data accesses, and interrupts. This has to be done in the scope of the target mission application at early design stages in order to minimize design bugs, reduce cost and optimize the design. In this work, we developed the system models of the RISC-V core and System-on-Chip (SoC) where the RISC-V cores were plugged in. Using the system model, we are able to run target applications/benchmarks on the RISC-V core and evaluate the performance and power for different clock frequencies, custom instructions, topology, cache associativity degrees, cache replacement policies, cache sizes, write-back policies, bus width, buffer sizes, bus speeds, memory types, and memory width. For each simulation, the system model generates various statistics including details on pipeline stalls, pipeline utilization, execution unit utilization, execution unit buffer occupancy, instruction and data cache accesses, cache hit ratio, number of evictions, writebacks, memory throughput, cycles per instruction, memory access latency and network latency. Using the system model, we were able to obtain debug logs from each SoC subsystem including the RISC-V cores. Using the pipeline traces for each instruction, we were able to verify the behavior of custom instructions which were introduced to improve our application performance. Performance and functional requirements were provided as input to the system model and faults were injected into the system model to determine the expected performance of the system under failure. Our SoC design was then updated to improve the fault tolerance and application performance by 4x times under faults by adding redundant cores and error correction mechanisms.","PeriodicalId":258620,"journal":{"name":"2023 IEEE Space Computing Conference (SCC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121388846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A System to Provide Deterministic Flight Software Operation and Maximize Multicore Processing Performance: The Safe and Precise Landing – Integrated Capabilities Evolution (SPLICE) Datapath","authors":"D. Rutishauser, John Prothro, Jordan Fail","doi":"10.1109/SCC57168.2023.00017","DOIUrl":"https://doi.org/10.1109/SCC57168.2023.00017","url":null,"abstract":"A method and design are described for a system that processes multiple data streams, utilizing a multicore asymmetric processing architecture, that eliminates data interrupts to the application processors. The design supports a deterministic environment for flight software in NASA’s Safe and Precise Landing – Integrated Capabilities Evolution (SPLICE) project. The SPLICE project develops sensor, algorithm, and compute technologies for Precision Landing and Hazard Avoidance (PL&HA) capabilities. The compute technology for SPLICE is the Descent and Landing Computer (DLC). The DLC hosts several SPLICE algorithms with high computational resource requirements that must be executed in a real-time and deterministic manner. The software runs on a custom Single Board Computer (SBC), with a Xilinx Ultrascale + Multiprocessor System-on-a-Chip (MPSoC). Input data for the flight software is from a variety of sensors, unique with respect to data rate and packet size. A data path between the SPLICE sensors and algorithms is designed to efficiently deliver this data to the flight software using the MPSoC asymmetric processing cores and Field Programmable Gate Array (FPGA) fabric. This is implemented in a manner that isolates the application processors running the flight software from interrupts associated with the input data. By leveraging real-time processors on the MPSoC, and a structure with the appropriate interfaces in the shared memory on the SBC, the flight software can use the full set of application processors. The available utilization for each processor in this set is also maximized for the SPLICE applications, providing a sufficiently deterministic execution environment without the cost and overhead of a real-time operating system.","PeriodicalId":258620,"journal":{"name":"2023 IEEE Space Computing Conference (SCC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123293011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Low Power And High Performance Software Approach to Artificial Intelligence On-Board","authors":"Pablo Ghiglino, M. Harshe","doi":"10.1109/SCC57168.2023.00019","DOIUrl":"https://doi.org/10.1109/SCC57168.2023.00019","url":null,"abstract":"New generations of spacecrafts are required to perform tasks with an increased level of autonomy. Space exploration, Earth Observation, space robotics, etc. are all growing fields in Space that require more sensors and more computational power to perform these missions. Furthermore, new sensors in the market produce better quality data at higher rates while new processors can increase substantially the computational power. Therefore, near-future spacecrafts will be equipped with large number of sensors that will produce data at rates that has not been seen before in space, while at the same time, data processing power will be significantly increased. Use cases like guidance navigation and control applications, vision-based navigation has become increasingly important in a variety of space applications for enhancing autonomy and dependability. Future missions such as Active Debris Removal will rely on novel high-performance avionics to support image processing and Artificial Intelligence algorithms with large workloads. Similar requirements come from Earth Observation applications, where data processing on-board can be critical in order to provide real-time reliable information to Earth. This new scenario of advanced Space applications and increase in data amount and processing power, has brought new challenges with it: low determinism, excessive power needs, data losses and large response latency. In this article, a novel approach to on-board artificial intelligence (AI) is presented that is based on state-of-the-art academic research of the well known technique of data pipeline. Algorithm pipelining has seen a resurgence in the high performance computing work due its low power use and high throughput capabilities. The approach presented here provides a very sophisticated threading model combination of pipeline and parallelization techniques applied to deep neural networks (DNN), making these type of AI applications much more efficient and reliable. This new approach has been validated with several DNN models developed for Space application (including asteroid landing, cloud detection and coronal mass ejection detection) and two different computer architectures. The results show that the data processing rate and power saving of the applications increase substantially with respect to standard AI solutions, enabling real AI on space.","PeriodicalId":258620,"journal":{"name":"2023 IEEE Space Computing Conference (SCC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116300447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"AI and Data-Driven In-situ Sensing for Space Digital Twin","authors":"Hyoshin Park, M. Ono, D. Posselt","doi":"10.1109/SCC57168.2023.00010","DOIUrl":"https://doi.org/10.1109/SCC57168.2023.00010","url":null,"abstract":"The formation and evolution of giant planets define the dominant characteristics of our planetary system. The giant-planet exploration can improve the understanding of heat flow, radiation balance, chemistry and can work as ground truth for exoplanets. Atmospheres of giant planets are larger and, in many respects, but simpler than that of Earth. Studying giant planets’ atmospheres and environments can serve as laboratories for the Earth atmosphere’s fundamental physical and dynamical processes. On the other hand, exploring the relevant environments that affect the Earth’s atmosphere can help us develop a sound technical and scientific basis in giant planets. Particularly, climate change on Earth is central to the question of understanding the roles of physics, geology, and dynamics in driving atmospheres and climates on Jupiter.","PeriodicalId":258620,"journal":{"name":"2023 IEEE Space Computing Conference (SCC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122231632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Benchmark Computer Performance for Wavefront Sensing and Control on Next Generation Space Telescopes","authors":"Nicholas Belsten, L. Pogorelyuk, K. Cahoy","doi":"10.1109/SCC57168.2023.00013","DOIUrl":"https://doi.org/10.1109/SCC57168.2023.00013","url":null,"abstract":"Future planned space telescopes, such as the HabEx and LUVOIR telescope concepts and the recently proposed Habitable Worlds Observatory, will use high contrast imaging and coronagraphy to directly image exoplanets for both detection and characterization. Such instruments will achieve the $sim 10wedge 10$ contrast level necessary for Earth-like exoplanet imaging by controlling thousands of actuators and sensing with thousands of pixels. Updates to the wavefront control actuators will need to be computed within seconds, placing unprecedented requirements on the real-time computational ability of radiation hardened processors. In this work we characterize the wavefront sensing and control algorithms to estimate the performance based on publicly available benchmark performance for currently available space-rated processors.","PeriodicalId":258620,"journal":{"name":"2023 IEEE Space Computing Conference (SCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130935660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}