2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM)最新文献_第6页

The Core Chip Design of Fast Locked All Digital Phase-locked Loop 快速锁相全数字锁相环核心芯片设计

2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2019-10-01 DOI: 10.1109/ICICM48536.2019.8977202

Yaqing Zhu, Lu Tang

引用次数: 1

Optimum Design of a New High Voltage Cascaded Amplifier Based on OPA454 基于OPA454的新型高压级联放大器的优化设计

2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2019-10-01 DOI: 10.1109/ICICM48536.2019.8977178

Hao Pan, Fangrong Zhou, Ke Wang, Yutang Ma, Hao Zhang, Chuan-Jin Zhang

{"title":"Optimum Design of a New High Voltage Cascaded Amplifier Based on OPA454","authors":"Hao Pan, Fangrong Zhou, Ke Wang, Yutang Ma, Hao Zhang, Chuan-Jin Zhang","doi":"10.1109/ICICM48536.2019.8977178","DOIUrl":"https://doi.org/10.1109/ICICM48536.2019.8977178","url":null,"abstract":"In order to obtain high linearity voltage signal with adjustable frequency, an optimal design scheme of high voltage cascaded linear amplifier based on OPA454 is proposed in this paper. Firstly, the main circuit, isolation circuit and cascade amplifier circuit of the high voltage cascade amplifier are designed. Then, the negative feedback characteristics and capacitive load characteristics of the linear amplifier are analyzed to ensure the high linearity and capacitive load capability of the output voltage signal. Finally, a two-stage cascade amplifier circuit model is built and tested in time domain at 0.001 Hz, 1.0 Hz and 1.0 kHz. The frequency response curves of the first-stage voltage amplifier circuit and the two-stage voltage amplifier circuit are compared in the frequency domain. The results show that the output voltage waveform of the new linear amplifier can be linearly amplified by 40n times of the input voltage, which achieves high linearity and low waveform distortion. It meets the requirement of accurate voltage amplification under adjustable frequency.","PeriodicalId":257536,"journal":{"name":"2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128025441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Numerical Study and Parametric optimization of Pin-Fin in the Microchannel Radiators with Hot Spots 带热点的微通道散热器引脚鳍的数值研究及参数优化

2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2019-10-01 DOI: 10.1109/ICICM48536.2019.8977196

W. Zhimin, Ye Guigen, Xue Shifeng, Gong Liang

引用次数: 2

Thermoelastic Damping in Bilayered Microbeam Resonators with Annular-cross Section 环形截面双层微束谐振腔的热弹性阻尼

2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2019-10-01 DOI: 10.1109/ICICM48536.2019.8977198

Zhijun Luo, Pu Li, Longfei Yang, Yuming Fang

引用次数: 0

Analysis of Partial Discharge Test of Transformer Caused by Excitation Transformer Fault 励磁变压器故障引起变压器局部放电试验分析

2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2019-10-01 DOI: 10.1109/ICICM48536.2019.8977148

Yu Bing, Zhao Lin, Yang Zhi, Yang Yong

{"title":"Analysis of Partial Discharge Test of Transformer Caused by Excitation Transformer Fault","authors":"Yu Bing, Zhao Lin, Yang Zhi, Yang Yong","doi":"10.1109/ICICM48536.2019.8977148","DOIUrl":"https://doi.org/10.1109/ICICM48536.2019.8977148","url":null,"abstract":"Partial discharge refers to a discharge phenomenon in which a portion of a region is discharged due to an electric field and there is no breakdown between the applied voltage conductors in an operating state. For transformers above 110kV, the partial discharge test is an effective means and method for verifying the insulation level of the transformer. Due to the limitations of the field test conditions, the partial discharge test of the transformer generally adopts a low-voltage side compensation press and a method of inducing a test voltage level on the high-voltage side. The state of the test equipment directly determines whether the experimental results meet the standard requirements. In this paper, we analyze the situation that the excitation is self-discharged and then transmitted to the transformer of the test, which results in the test result not meeting the standard requirements. At the same time, the excitation is returned to the factory for disintegration, and the cause of the accident is analyzed to provide experience and support for future field tests. During partial discharge test of transformer, the amount of partial discharge caused by the failure of the test equipment is difficult to distinguish. This type of problem can only be avoided by regular maintenance of the test equipment or by applying a voltage rise to the equipment.","PeriodicalId":257536,"journal":{"name":"2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116993221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Ultra-Low Noise Capacitive Readout Circuit for Gyroscopes 一种用于陀螺仪的超低噪声电容读出电路

2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2019-10-01 DOI: 10.1109/ICICM48536.2019.8977175

Yanfei Lu, Q. Duan, Zhen Meng, Shengming Huang, Yuemin Ding, Li Han

引用次数: 0

A Portable Fault Location Device for High Voltage Equipment Based on Acoustic Wave Method 一种基于声波法的便携式高压设备故障定位装置

2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2019-10-01 DOI: 10.1109/ICICM48536.2019.8977169

Wang Zezhou

引用次数: 0

A Module-Level Pipeline Implementation Based on Inter-Board Heterogeneous 基于板间异构的模块级流水线实现

2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2019-10-01 DOI: 10.1109/ICICM48536.2019.8977153

Haotian Liang, C. Shao, Haonan Qiang, Huiyun Li

{"title":"A Module-Level Pipeline Implementation Based on Inter-Board Heterogeneous","authors":"Haotian Liang, C. Shao, Haonan Qiang, Huiyun Li","doi":"10.1109/ICICM48536.2019.8977153","DOIUrl":"https://doi.org/10.1109/ICICM48536.2019.8977153","url":null,"abstract":"With the internet of things, autonomous driving, and smart security rapid development, data growth puts higher and more urgent requirements on processor computing performance. A single chip is hard to meet the real-time computing requirements in many scenarios, so it is necessary to expand multiple chips. This paper proposes a module-level pipeline FPGA cluster structure based on inter-board heterogeneous. The method divides a single enormous task into multiple modules and running each module on different FPGA as the pipeline structure between boards. In addition, considering the impact of communication delay between boards, it is proposed to use the delay between development boards as a separate stage of the pipeline. In this way, we can minimize a stage’s runtime of module level pipeline. In order to evaluate the calculate capacity of per hardware resource, the concept of resource conversion efficiency (RCE) is proposed. Experimental results of LeNet -5 neural network with the module-level pipeline structure design demonstrates that proposed method increased processing capacity and resource utilization efficiency. Compared with the method of sequential execution, the execution speed and RCE of the proposed method are increased by 46.1% and 84.7% respectively.","PeriodicalId":257536,"journal":{"name":"2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"2003 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125768400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The Influence of Working and Protective Grounding on Submarine Cable in AC Withstand Voltage Test 交流耐压试验中工作接地和保护接地对海底电缆的影响

2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2019-10-01 DOI: 10.1109/ICICM48536.2019.8977165

Haofan Lin, Yongtao Jin, Bing Yu, Lin Zhao, Yong Yang, Te Li

引用次数: 0

A High Gain and High CMRR Instrumentation Amplifier for Biomedical Applications 一种用于生物医学应用的高增益和高CMRR仪器放大器

2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2019-10-01 DOI: 10.1109/ICICM48536.2019.8977189

Ying-Yu Qian, Zhigong Wang, Yuekai Liu, Zhijun Zhou

{"title":"A High Gain and High CMRR Instrumentation Amplifier for Biomedical Applications","authors":"Ying-Yu Qian, Zhigong Wang, Yuekai Liu, Zhijun Zhou","doi":"10.1109/ICICM48536.2019.8977189","DOIUrl":"https://doi.org/10.1109/ICICM48536.2019.8977189","url":null,"abstract":"In this paper, an instrumentation amplifier (IA) based on operational amplifiers (op-amps) for biomedical applications is presented. Such IA achieves high gain and high common-mode rejection ratio (CMRR) while maintaining low power consumption, high power supply rejection ratio (PSRR) as well as other design constraints. The IA uses three identical two-stage telescopic cascode op-amps at the input and output stages. The feedback networks are comprised of resistors and capacitors, which are different from those in conventional voltage mode IA. The resistive feedback is utilized in the input stage to increase the stability while the capacitive feedback is employed in the output stage to filter undesired frequency components and enhance the gain of the IA. The schematic of IA is designed and simulated under 180 nm CMOS technology using Cadence Spectre tool. The gain and CMRR of the single op-amp are 100.45 dB and 94.8 dB respectively. The power consumed by each op-amp is 12.96 $mu mathrm{W}$ at a supply voltage of ± 0.9 V. RC Miller compensation technique helps the op-amp reaching a phase margin of 60°. This IA consumes a power of 38.88 $mu$W and CMRR of 147.68 dB, with a gain of 101.61 dB. The proposed technique is suitable for a variety of biomedical applications due to its high gain and high CMRR.","PeriodicalId":257536,"journal":{"name":"2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132535713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3