2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM)最新文献

ICICM 2019 Table of Contents ICICM 2019目录

2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2019-10-01 DOI: 10.1109/icicm48536.2019.8977157

引用次数: 0

Electrical Locating Technology for Failure Point Location Based on an Amplifier Module 基于放大器模块的故障点电气定位技术

2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2019-10-01 DOI: 10.1109/ICICM48536.2019.8977137

Zhimin Ding, Chao Duan, Xu Wang, Meng Meng, Zhibin Wang

引用次数: 0

[Copyright notice] (版权)

2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2019-10-01 DOI: 10.1109/icicm48536.2019.8977181

引用次数: 0

Memory optimization of CNN Heterogeneous Multi-Core Architecture CNN异构多核架构的内存优化

2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2019-10-01 DOI: 10.1109/ICICM48536.2019.8977143

Mingchen Gao, Dake Liu, Zhidong Miao, Shaohan Liu

{"title":"Memory optimization of CNN Heterogeneous Multi-Core Architecture","authors":"Mingchen Gao, Dake Liu, Zhidong Miao, Shaohan Liu","doi":"10.1109/ICICM48536.2019.8977143","DOIUrl":"https://doi.org/10.1109/ICICM48536.2019.8977143","url":null,"abstract":"Convolutional neural networks(CNNs) computing complexity raises challenges to the power and cost of CNN accelerators. The power consumption and delay of the data access between on-chip and off-chip memories have been a bottleneck of the on-chip system for CNN acceleration. We propose a static scheduling framework based on our heterogeneous programmable multi-core ASIP (Application Specific Instruction-set Processor) for inference of deep learning. This scheduling framework minimizes power consumption and promotes performance under the hardware resource limitation, including datapath computing capability, access bandwidth limitation, and on-chip memory size. We also discussed how to achieve theoretical maximum performance for a set of fixed hardware constraints. Comparing to the scheduling on DNA(deep neural architecture) under the same AlexNet platform, our scheduling achieves 11.8% more average resource utilization. By reusing and broadcasting local data, the average DRAM access of our design is reduced down to 41% of the access of DNA. The estimated power consumption of this design is 35% lower than the power of DNA, mostly because of the power reduction from DDR data accesses. Meanwhile, through the ping-pang memory and the careful design of data partition, the time of data access between DRAM and SRAM is reduced 77% by access hidden.","PeriodicalId":257536,"journal":{"name":"2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131448560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Research on Fault Prediction Method of Analog Circuits Based on DCQGA-SVR 基于DCQGA-SVR的模拟电路故障预测方法研究

2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2019-10-01 DOI: 10.1109/ICICM48536.2019.8977201

Xuelong Yan, Runping Ma

引用次数: 0

Influence of the Interface Charges' Location on the Threshold Voltage of TFT 界面电荷位置对TFT阈值电压的影响

2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2019-10-01 DOI: 10.1109/ICICM48536.2019.8977149

Ruize Sun, Zhun Zhang, Qi Yu, Jianming Cao

{"title":"Influence of the Interface Charges' Location on the Threshold Voltage of TFT","authors":"Ruize Sun, Zhun Zhang, Qi Yu, Jianming Cao","doi":"10.1109/ICICM48536.2019.8977149","DOIUrl":"https://doi.org/10.1109/ICICM48536.2019.8977149","url":null,"abstract":"With the development of VLSI (Very Large Scale Integration), the size of devices decreases and the electric field of gate oxide increases relatively. The degradation of TFT (Thin Film Transistor) devices is further affected by NBTI effect. When the device DB-NBTI degenerates, interface charges distribution is non-uniform. In this paper, the gate of p-type silicon TFT device is divided into several grid segments, and different concentration of interface charges is introduced to simulate the non-uniform distribution of charge. The relationship between the interface charges’ location and the threshold voltage is well simulated numerically, in which the conditions of drain biasing, interface charges’ concentration and with or without traps are considered. It is found that the device transfer characteristics lag behind those without considering the trap model. The influence of non-uniform interface charges on the threshold voltage of TFT is stronger near the source and weaker near the drain. When the drain voltage increases, the influence is suppressed to some extent. At the same time, the influence of interface charges on pMOS and TFT are compared and analyzed. The proposed work can promote the research on Drain Bias-Negative Bias Temperature Instability (DB-NBTI) effect.","PeriodicalId":257536,"journal":{"name":"2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"24 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131123929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Laser Modulation Driver in 130-nm CMOS Technology for Quantum Key Distribution System 一种用于量子密钥分配系统的130纳米CMOS激光调制驱动器

2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2019-10-01 DOI: 10.1109/ICICM48536.2019.8977145

Bo Feng, Futian Liang, Xinzhe Wang, Yulong Zhu, Chenxi Zhu, G. Jin

引用次数: 1

A New Generation of Static Timing Analysis Technology Based on N7+ Process—POCV 基于N7+工艺的新一代静态时序分析技术- pocv

2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2019-10-01 DOI: 10.1109/ICICM48536.2019.8977171

Xiaohong Peng, Hong Wang, Shengxia Wang, J. Du

引用次数: 2

A 50 GHz High Sensitivity InP HBT Comparator 一种50 GHz高灵敏度InP HBT比较器

2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2019-10-01 DOI: 10.1109/ICICM48536.2019.8977203

Hao Zhou, Youtao Zhang

引用次数: 0

A 71.8-87.9 GHz CMOS Injection-Locked Frequency Divider with Coupled Inductance 一种71.8-87.9 GHz耦合电感CMOS注入锁频分频器

2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2019-10-01 DOI: 10.1109/ICICM48536.2019.8977141

Jingyi Cai, Lu Tang

引用次数: 0