Xiaoyuan Zhang, Yi Zhang, Xincun Ji, Zhonghua Liu, Jian Xiao, Yu-feng Guo
{"title":"A 10-bit 320MS/s Time-Interleaved SAR ADC with an Improved Binary-Scaled Recombination Weighting Capacitor Array","authors":"Xiaoyuan Zhang, Yi Zhang, Xincun Ji, Zhonghua Liu, Jian Xiao, Yu-feng Guo","doi":"10.1109/ICICM48536.2019.8977177","DOIUrl":"https://doi.org/10.1109/ICICM48536.2019.8977177","url":null,"abstract":"This paper presents a 10-bit 320MS/s time-interleaved successive approximation register (SAR) ADC designed for WLAN (Wireless Local Area Network) applications. An improved binary-scaled recombination weighting capacitor array is disclosed in this work. The proposed SAR ADC achieves a SNDR of 59.9dB and an ENOB of 9.66 with Nyquist frequency at 1.2V and 320MS/s. The power dissipation is 2.2mW and the ADC core only occupies an area of 0.031mm2 in 40nm CMOS process.","PeriodicalId":257536,"journal":{"name":"2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128273772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Research on Fault Excitation Technology of Smart Meters","authors":"W. Shuang, Du Xiaomeng, Zhao Ting, W. Xiaodong","doi":"10.1109/ICICM48536.2019.8977179","DOIUrl":"https://doi.org/10.1109/ICICM48536.2019.8977179","url":null,"abstract":"When the voltage line of the smart meter is interrupted frequently, the emergency response capability of the hardware and software functions of the smart meter will be tested. The internal parameter setting, clock recording, metering performance and deduction function may be disordered. In order to test the emergency response capability and stimulate the potential failure of the smart meter, this paper designs a set of smart meter voltage response capability tests. Through the test, it is found that some manufacturers' smart meters have inaccurate measurement and communication interruption.","PeriodicalId":257536,"journal":{"name":"2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130162384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ming Ding, Donglin Liang, Anping He, Juxia Xiong, Jinzhao Wu
{"title":"A New Memory-Based Routing Policy for Mesh Network","authors":"Ming Ding, Donglin Liang, Anping He, Juxia Xiong, Jinzhao Wu","doi":"10.1109/ICICM48536.2019.8977195","DOIUrl":"https://doi.org/10.1109/ICICM48536.2019.8977195","url":null,"abstract":"We propose a new routing policy in Network on Chip (NoC) which is based on Memory. Compared with the data-based routing policy, the Memory-based routing policy can carry larger data volumes among the network and performs better routing efficiency. In the data-based NoC routing policy, data is routed among the network, but when data volumes are actually beyond data volumes carried by the network, the routing capacity of NoC network will be greatly reduced, and data congestion in the network will be caused. This problem does not only greatly reduce the routing efficiency of NoC network, but also causes data congestion in the network. In NoC, Mesh network is the main direction due to its simple topology, predictable routing path and strong network scalability. Therefore, taking Mesh network as an example, we combined Memory with Mesh network to implement the data-based routing policy. We also verify our design with FPGA successful.","PeriodicalId":257536,"journal":{"name":"2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131746170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Application and Comparison of the Contactless Overvoltage Measurement System Based on Integrated Electro-Optic Sensors","authors":"Ning Xu, Lin Zhao, Shaohe Wang, Yong Yang","doi":"10.1109/ICICM48536.2019.8977156","DOIUrl":"https://doi.org/10.1109/ICICM48536.2019.8977156","url":null,"abstract":"Effective monitoring of transient overvoltage is the key to field test, fault analysis and optimal design of power system. Traditional overvoltage measurement methods need to connect primary equipment to obtain signals, which is inconvenient and has security risks. A contactless overvoltage measurement system based on integrated electro-optic sensors (IEOSs) is introduced and applied in the field. The inductive electric field on IEOS is converted into optical signals with long-distance transmission and strong anti-interference ability. After modulation by the electric field to be measured, the phase difference information is carried into the photodetector and the output voltage of three-phase coupling is obtained. The measurement system has the advantages of no electrical connection with primary equipment, no additional power supply for sensors, wide frequency band and fast response. The coupling relationship of three-phase electric field is analyzed, and the decoupling strategy of output voltage waveform based on linear transformation is given. Finally, the field test results of this measurement system are compared with the waveforms recorded by the fault recorder, which verifies the effectiveness of the decoupling strategy. It also shows that the measurement system has good high frequency response characteristics.","PeriodicalId":257536,"journal":{"name":"2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125013783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ren Yanping, Shi Jiatao, Cheng Ke, Yu Shengjie, Z. Xin
{"title":"Study on the Effect of Liquid Cooling on the Temperature Distribution of Diesel Engine ECU","authors":"Ren Yanping, Shi Jiatao, Cheng Ke, Yu Shengjie, Z. Xin","doi":"10.1109/ICICM48536.2019.8977172","DOIUrl":"https://doi.org/10.1109/ICICM48536.2019.8977172","url":null,"abstract":"In this paper, an ECU simulation model of some kind of domestic diesel engine is established by using FloTHERM to study the effect of liquid cooling on ECU temperature distribution. Diesel is used as coolant in this paper. By changing the flow rate and temperature of the coolant, several comparative analyses were carried out, and it was found that the cooling effect of the liquid varied with the flow rate and temperature. The results show that liquid cooling can effectively reduce the temperature of ECU. Moreover, within the given range, the cooling effect increases with the increase of the flow rate, but the increase rate gradually decreased. And the temperature of ECU decreases linearly with the decrease of coolant temperature.","PeriodicalId":257536,"journal":{"name":"2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132212713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of Automated Voltage Protection Circuit for Digital DC-DC Switching Power Supply Digital-analog Hybrid Integrated System Design","authors":"D. Huo, Guojun Zhang","doi":"10.1109/ICICM48536.2019.8977167","DOIUrl":"https://doi.org/10.1109/ICICM48536.2019.8977167","url":null,"abstract":"Based on the research of digital DC-DC switching power management system, this paper uses arbitration scheduling circuit to perform segmental periodic overvoltage detection and undervoltage detection on the output voltage. When DPWM is ‘1’, overvoltage detection is turned on. When DPWM is ‘0’, undervoltage detection is turned on. This can reduce power consumption effectively. At the same time, on the basis of this, the detection signal is reported to the CPU for diagnosis. When the output voltage signal is wrong, the CPU will shut off the power supply of the entire system to achieve the purpose of automatic voltage protection. The new circuit structure proposed in this paper has the characteristics of low power consumption compared with the traditional analog circuit structure, and can realize the information interaction with the CPU to achieve precise logic control. Finally, the simulation was carried out using the 0.18um BCD process, and the ideal results were obtained.","PeriodicalId":257536,"journal":{"name":"2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133882718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Practical Estimation of Periodic Power Supply Induced Jitter for Clock Buffer Chains","authors":"Warren Anderson, Xiongliang Lai","doi":"10.1109/ICICM48536.2019.8977200","DOIUrl":"https://doi.org/10.1109/ICICM48536.2019.8977200","url":null,"abstract":"This paper presents a simple but practically accurate analytical closed-form expression for estimation of periodical power supply induced jitter (PSIJ) in MOS clock buffer chains. The closed-form expression is algebraically simple requiring only a few circuit simulation results without the pre-knowledge of circuit SPICE parameters. The expression predicts MOS clock buffer’s period PSIJ and N-Cycle PSIJ. Compared to SPICE simulated jitter, the closed-form expression predicts PSIJ with a maximum +30% error, which is generally sufficient for early-stage clock-buffer jitter budgeting before circuit implementations. The expression can be hand calculated and is well suited for IC design and application engineers to quickly summarize jitter tolerances for clock distribution networks in high-speed PHYs such as DDRs and SERDESes.","PeriodicalId":257536,"journal":{"name":"2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124794189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"ICICM 2019 Committees","authors":"","doi":"10.1109/icicm48536.2019.8977182","DOIUrl":"https://doi.org/10.1109/icicm48536.2019.8977182","url":null,"abstract":"","PeriodicalId":257536,"journal":{"name":"2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123142933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Real-Time Fast Path Network Processor for EtherCAT and Home Gateway","authors":"Xinbing Zhou, Dake Liu, P. Zhai, Shaohan Liu","doi":"10.1109/ICICM48536.2019.8977173","DOIUrl":"https://doi.org/10.1109/ICICM48536.2019.8977173","url":null,"abstract":"Network processors, also called protocol processors, are much used in mobile communications, broadband communications, and last mile accesses. Network processors are usually divided into fast path modules and slow path processors. Traditional fast path network modules are implemented as a configurable ASIC (Application Specific Integrated Circuit) with limited flexibility. In this paper, we designed and implemented a flexible fast path programmable network processor for EtherCAT real-time applications. The designed processor can also be used as fast path processors for home gateways being used up to 10GPON accesses. The processor is designed as an ASIP (Application Specific Instruction-set Processor) and it can be programmed for Ethernet, EtherCAT, IPv4, IPv6, UDP, and ARP. We are currently programming it to adapt to 5G layer two. The main contribution from the paper includes a fast path instruction set and its architecture. The performance of our instruction set is estimated more than 13 times faster than that of a single scaling general MCU.","PeriodicalId":257536,"journal":{"name":"2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"106 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123120151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Steady-State Thermal Simulation of the InP HBT Device Heat Spreading in DAHI Chip","authors":"Ming Wang, Youtao Zhang, Xiaopeng Li, Yi Zhang","doi":"10.1109/ICICM48536.2019.8977162","DOIUrl":"https://doi.org/10.1109/ICICM48536.2019.8977162","url":null,"abstract":"In this paper we analyzed the problem of thermal management in heterogeneous integration (InP HBT on CMOS). In this work because InP HBT chiplet is vertically stacked on the silicon chip, the heat from HBT devices can only be dissipated downward through the Si substrate. We performed 3-D finite element analysis to investigate the potential of thermal heterogeneous interconnect (THIC) as vertical heat spreader. The Diverse Accessible Heterogeneous Integration (DAHI) chip with the area of 2.7 $times$ 2.3m m2 is also analyzed by ANSYS. The simulation results show that THIC can effectively accelerate heat dissipation in DAHI chip, which will also improve the electric performance or reliability.","PeriodicalId":257536,"journal":{"name":"2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124180845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}