2009 IEEE International Conference on Computer Design最新文献_第7页

A new verification method for embedded systems 一种新的嵌入式系统验证方法

2009 IEEE International Conference on Computer Design Pub Date : 2009-10-04 DOI: 10.1109/ICCD.2009.5413154

Robert A. Thacker, C. Myers, K. R. Jones, S. Little

引用次数: 12

Efficient calibration of thermal models based on application behavior 基于应用行为的热模型的有效校准

2009 IEEE International Conference on Computer Design Pub Date : 2009-10-04 DOI: 10.1109/ICCD.2009.5413179

Youngwoo Ahn, Inchoon Yeo, R. Bettati

引用次数: 1

A power-aware hybrid RAM-CAM renaming mechanism for fast recovery 功率感知混合RAM-CAM重命名机制，用于快速恢复

2009 IEEE International Conference on Computer Design Pub Date : 2009-10-04 DOI: 10.1109/ICCD.2009.5413160

S. Petit, R. Ubal, J. Sahuquillo, P. López

引用次数: 4

Multiplier-less and table-less linear approximation for square and square-root 平方和平方根的无乘数和无表线性近似

2009 IEEE International Conference on Computer Design Pub Date : 2009-10-04 DOI: 10.1109/ICCD.2009.5413129

I. Park, Tae-Hwan Kim

引用次数: 14

Code density concerns for new architectures 新体系结构的代码密度问题

2009 IEEE International Conference on Computer Design Pub Date : 2009-10-04 DOI: 10.1109/ICCD.2009.5413117

Vincent M. Weaver, S. Mckee

引用次数: 21

A novel SoC architecture on FPGA for ultra fast face detection 一种基于FPGA的超快速人脸检测系统

2009 IEEE International Conference on Computer Design Pub Date : 2009-10-04 DOI: 10.1109/ICCD.2009.5413122

Chunhui He, Alexandros Papakonstantinou, Deming Chen

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引用次数: 56

The impact of liquid cooling on 3D multi-core processors 液体冷却对3D多核处理器的影响

2009 IEEE International Conference on Computer Design Pub Date : 2009-10-04 DOI: 10.1109/ICCD.2009.5413115

H. Jang, I. Yoon, C. Kim, Seungwon Shin, S. Chung

{"title":"The impact of liquid cooling on 3D multi-core processors","authors":"H. Jang, I. Yoon, C. Kim, Seungwon Shin, S. Chung","doi":"10.1109/ICCD.2009.5413115","DOIUrl":"https://doi.org/10.1109/ICCD.2009.5413115","url":null,"abstract":"Recently, 3D integration has been regarded as one of the most promising techniques due to its abilities of reducing global wire lengths and lowering power consumption. However, 3D integrated processors inevitably cause higher power density and lower thermal conductivity, since the closer proximity of heat generating dies makes existing thermal hotspots more severe. Without an efficient cooling method inside the package, 3D integrated processors should suffer severe performance degradation by dynamic thermal management as well as reliability problems. In this paper, we analyze the impact of the liquid cooling on a 3D multi-core processor compared to the conventional air cooling. We also evaluate the leakage power consumption and the lifetime reliability depending on the temperature of each functional unit in the 3D multi-core processor. The simulation results show that the liquid cooling reduces the temperature of the L1 instruction cache (the hottest block in this evaluation) by as much as 45 degrees, resulting in 12.8% leakage reduction, on average, compared to the conventional air cooling. Moreover, the reduced temperature of the L1 instruction cache also improves the reliability of electromigration, stress migration, time-dependent dielectric breakdown, thermal cycling, and negative bias temperature instability significantly.","PeriodicalId":256908,"journal":{"name":"2009 IEEE International Conference on Computer Design","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121208006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 34

3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis 使用缓存堆叠的3D GPU架构:性能、成本、功耗和热分析

2009 IEEE International Conference on Computer Design Pub Date : 2009-10-04 DOI: 10.1109/ICCD.2009.5413147

Ahmed Al-Maashri, Guangyu Sun, Xiangyu Dong, V. Narayanan, Yuan Xie

引用次数: 43

VariPipe: Low-overhead variable-clock synchronous pipelines VariPipe:低开销的可变时钟同步管道

2009 IEEE International Conference on Computer Design Pub Date : 2009-10-04 DOI: 10.1109/ICCD.2009.5413167

Navid Toosizadeh, S. Zaky, Jianwen Zhu

引用次数: 8

On-chip bidirectional wiring for heavily pipelined systems using network coding 片上双向布线重流水线系统使用网络编码

2009 IEEE International Conference on Computer Design Pub Date : 2009-10-04 DOI: 10.1109/ICCD.2009.5413165

Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, S. Khatri

{"title":"On-chip bidirectional wiring for heavily pipelined systems using network coding","authors":"Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, S. Khatri","doi":"10.1109/ICCD.2009.5413165","DOIUrl":"https://doi.org/10.1109/ICCD.2009.5413165","url":null,"abstract":"In this paper, we describe a low-area, reduced-power on-chip point-to-point bidirectional communication scheme for heavily pipelined systems. When data needs to be transmitted bidirectionally between two on-chip locations, the traditional approach resorts to either using two unidirectional wires, or to using a single wire (with a unidirectional transfer at any given time instant). In contrast, our bidirectional communication scheme allows data to be transmitted simultaneously between two on-chip locations, with a single wire performing the bidirectional data transfer. Our approach borrows ideas from the emerging area of network coding (in the field of communication). By utilizing coding units (which also serve the purpose of buffering the signals) along the wire between the two endpoints, we are able to achieve the same throughput as a traditional approach, while reducing the total area utilization by about 49.8% (thereby reducing routing congestion), and the total power consumption by about 11.5%. The area and power results include the contribution of routing wires, coding units, drivers, the clock distribution network and the required reset wire. Our bidirectional communication approach is ideally suited for heavily pipelined data intensive systems.","PeriodicalId":256908,"journal":{"name":"2009 IEEE International Conference on Computer Design","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124734797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3