2009 IEEE International Conference on Computer Design最新文献

Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs 基于tsv的三维soc中嵌入式内核的测试包装优化

2009 IEEE International Conference on Computer Design Pub Date : 2009-10-04 DOI: 10.1109/ICCD.2009.5413172

Brandon Noia, K. Chakrabarty, Yuan Xie

引用次数: 50

Performance analysis of decimal floating-point libraries and its impact on decimal hardware and software solutions 十进制浮点库的性能分析及其对十进制硬件和软件解决方案的影响

2009 IEEE International Conference on Computer Design Pub Date : 2009-10-04 DOI: 10.1109/ICCD.2009.5413114

Michael J. Anderson, C. Tsen, Liang-Kai Wang, Katherine Compton, M. Schulte

{"title":"Performance analysis of decimal floating-point libraries and its impact on decimal hardware and software solutions","authors":"Michael J. Anderson, C. Tsen, Liang-Kai Wang, Katherine Compton, M. Schulte","doi":"10.1109/ICCD.2009.5413114","DOIUrl":"https://doi.org/10.1109/ICCD.2009.5413114","url":null,"abstract":"The IEEE Standards Committee recently approved the IEEE 754–2008 Standard for Floating-point Arithmetic, which includes specifications for decimal floating-point (DFP) arithmetic. A growing number of DFP solutions have emerged, and developers now have many DFP design choices including arbitrary or fixed precision, binary or decimal significand encodings, 64-bit or 128-bit DFP operands, and software or hardware implementations. There is a need for accurate analysis of these solutions on representative DFP benchmarks. In this paper, we expand previous DFP benchmark and performance analysis research. We employ a DFP benchmark suite that currently supports several DFP solutions and is easily extendable. We also present performance analysis that (1) provides execution profiles for various DFP encodings and types, (2) gives the average number cycles for common DFP operations and the total number of each DFP operation in each benchmark, and (3) highlights the tradeoffs between using 64-bit and 128-bit DFP operands for both binary and decimal significand encodings. This analysis can help guide the design of future DFP hardware and software solutions.","PeriodicalId":256908,"journal":{"name":"2009 IEEE International Conference on Computer Design","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117190484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24

The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies 回收缓存:用于下一代内存技术的容错缓存架构

2009 IEEE International Conference on Computer Design Pub Date : 2009-10-04 DOI: 10.1109/ICCD.2009.5413145

Cheng-Kok Koh, W. Wong, Yiran Chen, Hai Helen Li

{"title":"The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies","authors":"Cheng-Kok Koh, W. Wong, Yiran Chen, Hai Helen Li","doi":"10.1109/ICCD.2009.5413145","DOIUrl":"https://doi.org/10.1109/ICCD.2009.5413145","url":null,"abstract":"There has been much work on the next generation of memory technologies such as MRAM, RRAM and PRAM. Most of these are non-volatile in nature, and compared to SRAM, they are often denser, just as fast, and have much lower energy consumption. Using 3-D stacking technology, it has been proposed that they can be used instead of SRAM in large level 2 caches prevalent in today's microprocessors. However, one of the key challenges in the use of these technologies, such as MRAM, is their higher fault probabilities arising from the larger process variation, defects in its fabrication, and the fact that the cache is much larger. This seriously affect yield. In this paper, we propose a fault resilient set associative cache architecture which we called the salvage cache. In the salvage cache, a faulty cache block is sacrificed and used to repair faults found in other blocks. We will describe in detail the architecture of the salvage cache as well as provide results of yield simulations that show that a much higher yield can be achieved viz-a-viz other fault tolerant techniques. We will also show the performance savings that arise from the use of a large next-generation L2 cache.","PeriodicalId":256908,"journal":{"name":"2009 IEEE International Conference on Computer Design","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115560292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 28

A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes 一个技术不可知的仿真环境(TASE)迭代定制集成电路设计的过程

2009 IEEE International Conference on Computer Design Pub Date : 2009-10-04 DOI: 10.1109/ICCD.2009.5413107

Satyanand Nalam, M. Bhargava, Kyle Ringgenberg, K. Mai, B. Calhoun

{"title":"A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes","authors":"Satyanand Nalam, M. Bhargava, Kyle Ringgenberg, K. Mai, B. Calhoun","doi":"10.1109/ICCD.2009.5413107","DOIUrl":"https://doi.org/10.1109/ICCD.2009.5413107","url":null,"abstract":"A designer's intent and knowledge about the critical issues and trade-offs underlying a custom circuit design are implicit in the simulations she sets up for design creation and verification. However, this knowledge is tightly conjoined with technology-specific features and decoupled from the final schematic in traditional design flows. As a result, this knowledge is easily lost when the technology specifics change. This paper presents a Technology Agnostic Simulation Environment (TASE), which is a tool that uses simulation templates to capture the designer's knowledge and separate it from the technology-specific components of a simulation. TASE also allows the designer to form groups of related simulations and port them as a unit to a new technology. This allows an actual design schematic to remain tied to the analyses that illuminate the underlying trade-offs and design issues, unlike the case where schematics are ported alone. Giving the designer immediate access to the trade-offs, which are likely to change in new technologies, accelerates the re-design that often must accompany porting of complicated custom circuits. We demonstrate the usefulness of TASE by investigating Read and Write noise margins for a 6T SRAM in predictive technologies down to 16 nm.","PeriodicalId":256908,"journal":{"name":"2009 IEEE International Conference on Computer Design","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114180877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Low-overhead error detection for Networks-on-Chip 片上网络的低开销错误检测

2009 IEEE International Conference on Computer Design Pub Date : 2009-10-04 DOI: 10.1109/ICCD.2009.5413150

A. Berman, I. Keidar

引用次数: 7

3D stacked power distribution considering substrate coupling 考虑衬底耦合的三维叠加功率分布

2009 IEEE International Conference on Computer Design Pub Date : 2009-10-04 DOI: 10.1109/ICCD.2009.5413151

A. S. Arani, Xiang Hu, Wanping Zhang, Chung-Kuan Cheng, A. Engin, Xiaoming Chen, M. Popovich

引用次数: 20

Framework for massively parallel testing at wafer and package test 用于晶圆和封装测试的大规模并行测试框架

2009 IEEE International Conference on Computer Design Pub Date : 2009-10-04 DOI: 10.1109/ICCD.2009.5413134

A. H. Baba, Kee Sup Kim

引用次数: 9

Fault-tolerant synthesis using non-uniform redundancy 使用非均匀冗余的容错综合

2009 IEEE International Conference on Computer Design Pub Date : 2009-10-04 DOI: 10.1109/ICCD.2009.5413153

Keven L. Woo, Matthew R. Guthaus

引用次数: 9

Hierarchical parametric test metrics estimation: A ΣΔ converter BIST case study 分层参数测试度量估计:ΣΔ转换器BIST案例研究

2009 IEEE International Conference on Computer Design Pub Date : 2009-10-04 DOI: 10.1109/ICCD.2009.5413173

M. Dubois, H. Stratigopoulos, S. Mir

引用次数: 9

A distributed concurrent on-line test scheduling protocol for many-core NoC-based systems 面向多核计算机系统的分布式并发在线测试调度协议

2009 IEEE International Conference on Computer Design Pub Date : 2009-10-04 DOI: 10.1109/ICCD.2009.5413156

J. Lee, R. Mahapatra, Praveen Bhojwani

{"title":"A distributed concurrent on-line test scheduling protocol for many-core NoC-based systems","authors":"J. Lee, R. Mahapatra, Praveen Bhojwani","doi":"10.1109/ICCD.2009.5413156","DOIUrl":"https://doi.org/10.1109/ICCD.2009.5413156","url":null,"abstract":"Concurrent on-line testing (COLT) of many-core systems-on-chip (SoC) has been recently proposed by researchers in response to the growing threat of electronic wear-out to system operational lifetimes and to the increasing reliability and availability demands of safety-critical applications. Previous research in concurrent on-line testing has focused on centralized approaches to manage core testing while the system is available to execute normal user applications. However, as technology scaling allows dozens and hundreds of processing cores to be placed on a single chip, these centralized approaches are not scalable solutions. In this paper, a distributed concurrent on-line test scheduling protocol is proposed and evaluated against previously developed solutions. Our experiments show that a distributed COLT scheduler can test a moderately-sized SoC with a speedup of 3.85 over centralized approaches while consuming 84% less energy, and performance benefits improve as the number of cores per chip increases. This research also presents a core test ordering algorithm — Code-Division Core Test Scheduling — that provides an additional 40% reduction in system test latency compared to other schedulers.","PeriodicalId":256908,"journal":{"name":"2009 IEEE International Conference on Computer Design","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131129329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1