{"title":"用于晶圆和封装测试的大规模并行测试框架","authors":"A. H. Baba, Kee Sup Kim","doi":"10.1109/ICCD.2009.5413134","DOIUrl":null,"url":null,"abstract":"A novel DFT approach is introduced that enables massively parallel testing of logic devices at both wafer and package test. Parallelism is achieved by utilizing interconnection networks that are built onto a wafer probe or a tester interface unit. The financial benefits of this method in a realistic setting are also presented.","PeriodicalId":256908,"journal":{"name":"2009 IEEE International Conference on Computer Design","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Framework for massively parallel testing at wafer and package test\",\"authors\":\"A. H. Baba, Kee Sup Kim\",\"doi\":\"10.1109/ICCD.2009.5413134\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel DFT approach is introduced that enables massively parallel testing of logic devices at both wafer and package test. Parallelism is achieved by utilizing interconnection networks that are built onto a wafer probe or a tester interface unit. The financial benefits of this method in a realistic setting are also presented.\",\"PeriodicalId\":256908,\"journal\":{\"name\":\"2009 IEEE International Conference on Computer Design\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-10-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE International Conference on Computer Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCD.2009.5413134\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE International Conference on Computer Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCD.2009.5413134","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Framework for massively parallel testing at wafer and package test
A novel DFT approach is introduced that enables massively parallel testing of logic devices at both wafer and package test. Parallelism is achieved by utilizing interconnection networks that are built onto a wafer probe or a tester interface unit. The financial benefits of this method in a realistic setting are also presented.
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