Proceedings of the 25th edition on Great Lakes Symposium on VLSI最新文献_第7页

Untrusted Third Party Digital IP Cores: Power-Delay Trade-off Driven Exploration of Hardware Trojan Secured Datapath during High Level Synthesis 不受信任的第三方数字IP核:在高级合成过程中硬件木马安全数据路径的功率延迟权衡驱动探索

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742061

A. Sengupta, Saumya Bhadauria

{"title":"Untrusted Third Party Digital IP Cores: Power-Delay Trade-off Driven Exploration of Hardware Trojan Secured Datapath during High Level Synthesis","authors":"A. Sengupta, Saumya Bhadauria","doi":"10.1145/2742060.2742061","DOIUrl":"https://doi.org/10.1145/2742060.2742061","url":null,"abstract":"An evolutionary algorithm (EA) driven novel design space exploration (DSE) of an optimized hardware Trojan secured datapath based on user power-delay constraint during high level synthesis (HLS) is presented. The focus on hardware Trojan secured datapath generation during HLS has been very little with absolutely zero effort so far in design space exploration of a user multi-objective (MO) constraint optimized hardware Trojan secured datapath. This problem mandates attention as producing a Trojan secured datapath is not inconsequential. Merely the detection process of Trojan is not as straightforward as concurrent error detection (CED) of transient faults as it involves the concept of multiple third party intellectual property (3PIP) vendors to facilitate detection, let aside the exploration process of a user optimized Trojan secured datapath based on MO constraints. The proposed DSE for hardware Trojan detection includes novel problem encoding technique that enables exploration of efficient distinct vendor allocation as well as enables exploration of an optimized Trojan secured datapath structure. The exploration backbone for the proposed approach is bacterial foraging optimization algorithm (BFOA) which is known for its adaptive feature (tumbling/swimming) and simplified model. Results of comparison with recent approach indicated an average improvement in quality of results (QoR) of >14.1%","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133254911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

Layout Characterization and Power Density Analysis for Shorted-Gate and Independent-Gate 7nm FinFET Standard Cells 短栅和独立栅7nm FinFET标准电池的布局表征和功率密度分析

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742093

Tiansong Cui, Bowen Chen, Yanzhi Wang, Shahin Nazarian, Massoud Pedram

引用次数: 5

Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization 通过合成后优化开发石墨烯可重构门的表达能力

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742098

S. Miryala, V. Tenace, A. Calimera, E. Macii, M. Poncino, L. Amarù, G. Micheli, P. Gaillardon

{"title":"Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization","authors":"S. Miryala, V. Tenace, A. Calimera, E. Macii, M. Poncino, L. Amarù, G. Micheli, P. Gaillardon","doi":"10.1145/2742060.2742098","DOIUrl":"https://doi.org/10.1145/2742060.2742098","url":null,"abstract":"As an answer to the new electronics market demands, semiconductor industry is looking for different materials, new process technologies and alternative design solutions that can support Silicon replacement in the VLSI domain. The recent introduction of graphene, together with the option of electrostatically controlling its doping profile, has shown a possible way to implement fast and power efficient Reconfigurable Gates (RGs). Also, and this is the most important feature considered in this work, those graphene RGs show higher expressive power, i.e., they implement more complex functions, like Majority, MUX, XOR, with less area w.r.t. CMOS counterparts. Unfortunately, state-of-the-art synthesis tools, which have been customized for standard NAND/NOR CMOS gates, do not exploit the aforementioned feature of graphene RGs. In this paper, we present a post-synthesis tool that translates the gate level netlist obtained from commercial synthesis tools to a more optimized netlist that can efficiently integrate graphene RGs. Results conducted on a set of open-source benchmarks demonstrate that the proposed strategy improves, on average, both area and performance by 17% and 8.17% respectively.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125194653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Delay, Power and Energy Tradeoffs in Deep Voltage-scaled FPGAs 深电压级fpga的延迟、功率和能量权衡

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742120

M. Abusultan, S. Khatri

引用次数: 1

Statistically Validating the Impact of Process Variations on Analog and Mixed Signal Designs 统计验证过程变化对模拟和混合信号设计的影响

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742122

Ibtissem Seghaier, M. Zaki, S. Tahar

引用次数: 4

Reconfigurable: Self Adaptive Fault Tolerant Cache Memory for DVS enabled Systems 可重构:为启用分布式交换机的系统提供自适应容错缓存

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742091

Michail Mavropoulos, G. Keramidas, Grigorios Adamopoulos, D. Nikolos

{"title":"Reconfigurable: Self Adaptive Fault Tolerant Cache Memory for DVS enabled Systems","authors":"Michail Mavropoulos, G. Keramidas, Grigorios Adamopoulos, D. Nikolos","doi":"10.1145/2742060.2742091","DOIUrl":"https://doi.org/10.1145/2742060.2742091","url":null,"abstract":"Processor caches play a critical role in the performance of today\"s computer systems. As technology scales, due to manufacturing defects and process variations a large number of cells in a cache is expected to be faulty. The number of faulty cells varies from die to die and in the field of the application depends on the operating conditions (e.g., supply voltage, frequency). Several techniques have been proposed to tolerate faults in caches. A drawback of the redundancy based techniques is that the amount of redundancy is decided at the design time targeting a maximum number of faults, so in cases of a small number of faults (e.g., in the nominal supply voltage in a system with DVS) only a part of the redundant resources is used. In this paper we propose a new reconfigurable-self adaptive fault tolerant cache scheme. The unique characteristic of our scheme is that it uses its resources for both the reduction of the misses caused by the faulty blocks as well as for the reduction of conflict misses, depending on the number of faults, their distribution in the cache, and the running application. Our experimental results for a wide range of scientific applications and a plethora of fault maps with different SRAM failure probabilities reveal that our proposal can achieve significant benefits.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128008853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Origami: A Convolutional Network Accelerator 折纸:卷积网络加速器

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2743766

L. Cavigelli, David Gschwend, Christoph Mayer, Samuel Willi, Beat Muheim, L. Benini

引用次数: 149

Design Automation for Biological Models: A Pipeline that Incorporates Spatial and Molecular Complexity 生物模型设计自动化:整合空间和分子复杂性的管道

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2743763

Devin P. Sullivan, Rohan Arepally, R. Murphy, J. Tapia, J. Faeder, M. Dittrich, J. Czech

引用次数: 6

A Multilayered Design Approach for Efficient Hybrid 3D Photonics Network-on-chip 一种高效混合三维光子学片上网络的多层设计方法

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742083

Dharanidhar Dang, B. Patra, R. Mahapatra

引用次数: 6

Dynamic Power Reduction Techniques in On-Chip Photonic Interconnects 片上光子互连中的动态功耗降低技术

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742118

B. Neel, M. Kennedy, Avinash Karanth Kodi

引用次数: 10