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Proceedings of Electrical Performance of Electronic Packaging最新文献

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The impedance transformation technique for the elimination of numerical errors in the simulation of power/ground plane noise 阻抗变换技术用于消除功率/地平面噪声仿真中的数值误差
Proceedings of Electrical Performance of Electronic Packaging Pub Date : 1995-10-02 DOI: 10.1109/EPEP.1995.524859
Zhonghua Wu, J. Fang
{"title":"The impedance transformation technique for the elimination of numerical errors in the simulation of power/ground plane noise","authors":"Zhonghua Wu, J. Fang","doi":"10.1109/EPEP.1995.524859","DOIUrl":"https://doi.org/10.1109/EPEP.1995.524859","url":null,"abstract":"In the simulation of power/ground plane noise in electronic packaging, certain numerical errors are introduced in discretizing metal planes by numerical meshes. This paper presents the impedance transformation technique that eliminates such numerical errors. An impedance transformer used to transform the input impedance of an arbitrary rectangular finite-difference mesh to the input impedance of the physical structure composed of power and ground planes is presented. Numerical verification of the closed form solution is also provided.","PeriodicalId":253331,"journal":{"name":"Proceedings of Electrical Performance of Electronic Packaging","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125585812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Optoelectronic packaging for data communications: Optical and electrical modeling needs for cost-effective designs 用于数据通信的光电封装:成本效益设计的光学和电气建模需求
Proceedings of Electrical Performance of Electronic Packaging Pub Date : 1995-10-02 DOI: 10.1109/EPEP.1995.524877
K. Jackson
{"title":"Optoelectronic packaging for data communications: Optical and electrical modeling needs for cost-effective designs","authors":"K. Jackson","doi":"10.1109/EPEP.1995.524877","DOIUrl":"https://doi.org/10.1109/EPEP.1995.524877","url":null,"abstract":"Fiber-optic data links, based on CD-type short wavelength (/spl lambda/=780 nm) lasers and multimode optical fibers are beginning to emerge as viable solutions for high performance, low cost computer interconnects. This presentation will describe the technology and discuss some key areas where better modeling is needed to enable more precise cost/performance trade-offs to be made.","PeriodicalId":253331,"journal":{"name":"Proceedings of Electrical Performance of Electronic Packaging","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116841581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A COPLANAR WAVEGUIDE PROBE WITH APPLICATIONS TO THIN FILM DIELECTRIC MEASUREMENTS 一种用于薄膜介电测量的共面波导探头
Proceedings of Electrical Performance of Electronic Packaging Pub Date : 1995-10-02 DOI: 10.1109/EPEP.1995.524872
E.W. Seltmann, J. Laskar, K. Smith, R. Gleason
{"title":"A COPLANAR WAVEGUIDE PROBE WITH APPLICATIONS TO THIN FILM DIELECTRIC MEASUREMENTS","authors":"E.W. Seltmann, J. Laskar, K. Smith, R. Gleason","doi":"10.1109/EPEP.1995.524872","DOIUrl":"https://doi.org/10.1109/EPEP.1995.524872","url":null,"abstract":"A novel approach to thin film dielectric measurements at microwave and millimeter wave frequencies is investigated using a coplanar waveguide (CPW) probe. Using the spectral-domain technique, an admittance model describing the CPW thin film interface system is determined for reflection measurement techniques, and delay measurement analysis is performed for thru measurement techniques. To validate the model, an error analysis is performed with 3D electromagnetic simulators and CPW S-parameter data from materials with known dielectric properties.","PeriodicalId":253331,"journal":{"name":"Proceedings of Electrical Performance of Electronic Packaging","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116480927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Challenges raised by long on-chip wiring for CMOS microprocessor applications CMOS微处理器应用的长片上布线带来的挑战
Proceedings of Electrical Performance of Electronic Packaging Pub Date : 1995-10-02 DOI: 10.1109/EPEP.1995.524683
A. Deutsch, G. Kopcsay, C. Surovic, B. Rubin, L. Terman, R. P. Dunne, T. Gallo
{"title":"Challenges raised by long on-chip wiring for CMOS microprocessor applications","authors":"A. Deutsch, G. Kopcsay, C. Surovic, B. Rubin, L. Terman, R. P. Dunne, T. Gallo","doi":"10.1109/EPEP.1995.524683","DOIUrl":"https://doi.org/10.1109/EPEP.1995.524683","url":null,"abstract":"The unique characteristics of long on-chip interconnections in terms of modelling, simulation and design practices are investigated for representative five-layer structures. Experimental results are shown for a specially designed test vehicle with lines as long as 1.6 cm and line resistance of R=35 to 500 /spl Omega//cm.","PeriodicalId":253331,"journal":{"name":"Proceedings of Electrical Performance of Electronic Packaging","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116501216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Design and packaging of antennas for wireless systems 无线系统天线的设计与封装
Proceedings of Electrical Performance of Electronic Packaging Pub Date : 1995-10-02 DOI: 10.1109/EPEP.1995.524881
Yorktown Ilciglits
{"title":"Design and packaging of antennas for wireless systems","authors":"Yorktown Ilciglits","doi":"10.1109/EPEP.1995.524881","DOIUrl":"https://doi.org/10.1109/EPEP.1995.524881","url":null,"abstract":"Mobile RF systems may consist of single or multiple links between stationary base units, and mobile remote units. The stationary base and mobile remote antennas are almost always mounted on the chassis which contains the radio and/or other electronics. The remote tends to be compact in size, and aside from form factor constraints for the remote antenna, one of the key specifications is that it radiate omnidirectionally in the horizontal plane, so that a stable communication link can be established with a base unit in any direction. An omnidirectional pattern may or may not be a requirement for the base antenna, depending on how base station \"cells\" are structured. EMC and EMI considerations require that packaging for the remote and base have adequate shielding, for inner electronics and prevent radiation leakage outside the chassis. Consequently the chassis are coated with a conductive paint, and/or conductive shields are present. The external packaging can cause \"shadowing\", in which the radiation pattern to becomes directive or has deep nulls, or call \"detune\" the antenna, in which the impedance seen at the antenna input terminals is altered, or can significantly effect antenna gain. Simultaneously meeting antenna and package goals presents an interesting challenge from an antenna and package design point of view. In this paper, antenna design is discussed with a focus on the impact of packaging on radiation characteristics, and physical design of antennas in order to best meet specifications.","PeriodicalId":253331,"journal":{"name":"Proceedings of Electrical Performance of Electronic Packaging","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134555030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
High quality-factor inductors integrated on Si multichip modules 集成在Si多芯片模块上的高质量因数电感
Proceedings of Electrical Performance of Electronic Packaging Pub Date : 1995-10-02 DOI: 10.1109/EPEP.1995.524882
L. Zu, Yicheng Lu, R. Frye, M. Lau, S. Chen, D. Kossives, F. Hrycenko, Jenshan Lin, Qing Lin, K. Tai
{"title":"High quality-factor inductors integrated on Si multichip modules","authors":"L. Zu, Yicheng Lu, R. Frye, M. Lau, S. Chen, D. Kossives, F. Hrycenko, Jenshan Lin, Qing Lin, K. Tai","doi":"10.1109/EPEP.1995.524882","DOIUrl":"https://doi.org/10.1109/EPEP.1995.524882","url":null,"abstract":"We report high quality (Q) factor inductors fabricated on a high-resistivity (2000 /spl Omega/-cm) Si substrate with MCM technology. Q-factors of 30-40 were achieved for inductors of a few nH at 1 GHz.","PeriodicalId":253331,"journal":{"name":"Proceedings of Electrical Performance of Electronic Packaging","volume":"29 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131703448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Low cost 400 MHz source synchronous data links 低成本400兆赫源同步数据链路
Proceedings of Electrical Performance of Electronic Packaging Pub Date : 1995-10-02 DOI: 10.1109/EPEP.1995.524878
R. Nikel
{"title":"Low cost 400 MHz source synchronous data links","authors":"R. Nikel","doi":"10.1109/EPEP.1995.524878","DOIUrl":"https://doi.org/10.1109/EPEP.1995.524878","url":null,"abstract":"Design of low cost high speed interconnect is a challenge that faces system designers. A method for designing and modeling a 400 MHz CMOS system interconnect is discussed. Detailed measurements of signal quality and interconnect are presented.","PeriodicalId":253331,"journal":{"name":"Proceedings of Electrical Performance of Electronic Packaging","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126589148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A new flat spiral routing to minimize crosstalk penalty in delay line 一种新的平螺旋布线，以减少延迟线的串扰损失
Proceedings of Electrical Performance of Electronic Packaging Pub Date : 1995-10-02 DOI: 10.1109/EPEP.1995.524895
R. Wu, F. Chao
{"title":"A new flat spiral routing to minimize crosstalk penalty in delay line","authors":"R. Wu, F. Chao","doi":"10.1109/EPEP.1995.524895","DOIUrl":"https://doi.org/10.1109/EPEP.1995.524895","url":null,"abstract":"This paper proposes a novel flat spiral routing scheme for the planar delay line to minimize the signal distortion and delay time penalty incurred by backward propagating crosstalk among the parallel sections of delay line.","PeriodicalId":253331,"journal":{"name":"Proceedings of Electrical Performance of Electronic Packaging","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132943620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Delay time estimate for "FAST" CMOS drivers with noisy ground reference 具有噪声地参考的“FAST”CMOS驱动器的延迟时间估计
Proceedings of Electrical Performance of Electronic Packaging Pub Date : 1995-10-02 DOI: 10.1109/EPEP.1995.524690
Yaochao Yang, Aritharan Thurairajaratnam, J. Brews, J. Prince
{"title":"Delay time estimate for \"FAST\" CMOS drivers with noisy ground reference","authors":"Yaochao Yang, Aritharan Thurairajaratnam, J. Brews, J. Prince","doi":"10.1109/EPEP.1995.524690","DOIUrl":"https://doi.org/10.1109/EPEP.1995.524690","url":null,"abstract":"A closed form equation to predict the signal delay of high speed CMOS drivers as a function of the Simultaneous Switching Noise (SSN) has been derived. This delay estimate agrees with the results obtained from SPICE simulations with typical driver strengths and load capacitances.","PeriodicalId":253331,"journal":{"name":"Proceedings of Electrical Performance of Electronic Packaging","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133796941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
FREQUENCY DOMAIN MEASUREMENTS OF VSPA: A NOVEL PACKAGING TECHNOLOGY vspa频域测量:一种新型封装技术
Proceedings of Electrical Performance of Electronic Packaging Pub Date : 1995-10-02 DOI: 10.1109/EPEP.1995.524875
J. Hao, A. Richter, J. Laskar, M. Swaminathan, J. Mosley
{"title":"FREQUENCY DOMAIN MEASUREMENTS OF VSPA: A NOVEL PACKAGING TECHNOLOGY","authors":"J. Hao, A. Richter, J. Laskar, M. Swaminathan, J. Mosley","doi":"10.1109/EPEP.1995.524875","DOIUrl":"https://doi.org/10.1109/EPEP.1995.524875","url":null,"abstract":"This paper describes the modeling and measurement of VSPA, a very small peripheral array package developed by Archistrat containing 320 pins with a size of 27 mm/spl times/27 mm. The analysis covers a frequency range of 20 MHz-3 GHz, includes analytical calculations, simulations, measurements, leading to a lumped model representation of the package parasitics.","PeriodicalId":253331,"journal":{"name":"Proceedings of Electrical Performance of Electronic Packaging","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115429307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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