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International Conferencre on Simulation of Semiconductor Processes and Devices最新文献

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Investigation of the electron mobility in strained Si/sub 1-x/Ge/sub x/ at high Ge composition 高锗成分下Si/sub - 1-x/Ge/sub -x/应变中电子迁移率的研究
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034509
S. Smirnov, H. Kosina, S. Selberherr
{"title":"Investigation of the electron mobility in strained Si/sub 1-x/Ge/sub x/ at high Ge composition","authors":"S. Smirnov, H. Kosina, S. Selberherr","doi":"10.1109/SISPAD.2002.1034509","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034509","url":null,"abstract":"Monte Carlo simulation of the low field electron mobility of strained Si and SiGe active layers on SiGe substrate is considered. The Ge mole fractions of both the active layer and the substrate are varied in a wide range. The linear deformation potential theory is used to calculate the shifts of the conduction band minima due to the uniaxial strain along [001]. The energy shifts and the effective masses are assumed to be functions of the Ge mole fraction. Finally, the ionized impurity scattering rate is generalized to include strain effects for doped materials.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116818429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Coupled-field modeling of microdevices and microsystems 微器件和微系统的耦合场建模
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034505
G. Wachutka
{"title":"Coupled-field modeling of microdevices and microsystems","authors":"G. Wachutka","doi":"10.1109/SISPAD.2002.1034505","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034505","url":null,"abstract":"Currently strong efforts are being made to build simulation platforms for the predictive simulation of microelectromechanical devices and microsystems (MEMS) as cost-effective and time-saving alternative to the traditional experimental approach. Already today the rapid progress in microsystems technology is strongly supported by MEMS-specific modeling methodologies and dedicated simulation tools constituting a \"virtual laboratory\" on the computer, which enables the visualization and detailed analysis of the operating behavior of single microdevices as well as their collaborative function in a microsystem. In this context, one of the most important aspects is the consistent treatment of coupled fields and coupled energy and signal domains required for deriving macromodels of microsystems from the continuous field level. To this end, we discuss practicable methodologies for setting up physically-based consistent microdevice and full system models for the effort-economizing and yet accurate numerical simulation of micro-mechatronical components and systems.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122367846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Transistor width dependence of LER degradation to CMOS device characteristics 晶体管宽度对二极管衰减特性的依赖性
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034525
J. Wu, Jihong Chen, Kaiping Liu
{"title":"Transistor width dependence of LER degradation to CMOS device characteristics","authors":"J. Wu, Jihong Chen, Kaiping Liu","doi":"10.1109/SISPAD.2002.1034525","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034525","url":null,"abstract":"When transistor gate length is scaled down, the impact of transistor poly gate line edge roughness (LER) on device characteristics becomes significant. In this work, we study the dependence on transistor width of the low spatial frequency LER induced CMOS device Ion/Ioff degradations, based on TCAD simulation results and silicon data. Methodology to account for LER effects in device optimization is also discussed. We found that when the transistor width becomes comparable to the LER spatial period, the resulting transistor Ion/Ioff degradation presents a very different signature from that of wide transistor cases. We found that for narrow width transistors, the scatter clouds on the Ion/Ioff plot stretch out along the Ion/Ioff curve direction and compress vertically toward the ideal Ion/Ioff curve resulting in transistor parametric yield loss.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130647821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
The process modeling hierarchy: connecting atomistic calculations to nanoscale behavior 过程建模层次:将原子计算与纳米级行为联系起来
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034555
S. Dunham
{"title":"The process modeling hierarchy: connecting atomistic calculations to nanoscale behavior","authors":"S. Dunham","doi":"10.1109/SISPAD.2002.1034555","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034555","url":null,"abstract":"In this work, we review efforts to make effective use of atomistic calculations for the advancement of VLSI process simulation.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130924647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Simulation technique of heating by contact resistance for ESD protection device 静电放电保护装置接触电阻发热模拟技术
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034531
K. Matsuzawa, H. Kawashima, T. Matsuhashi, S. Yasuda
{"title":"Simulation technique of heating by contact resistance for ESD protection device","authors":"K. Matsuzawa, H. Kawashima, T. Matsuhashi, S. Yasuda","doi":"10.1109/SISPAD.2002.1034531","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034531","url":null,"abstract":"An appropriate treatment of the contact resistance in device simulation is presented for the purpose of studying thermal immunity of ESD protection devices. The technique presented allows the appropriate resistivity and power density to be provided at the contact. The validity of the power density around the contact is checked by Monte Carlo simulation. Using the technique, influence of the contact resistance on self-heating in an ESD protection device is simulated.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132460203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
In-advance CPU time analysis for Monte Carlo device simulations 蒙特卡罗设备模拟的提前CPU时间分析
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034527
C. Jungemann, B. Meinerzhagen
{"title":"In-advance CPU time analysis for Monte Carlo device simulations","authors":"C. Jungemann, B. Meinerzhagen","doi":"10.1109/SISPAD.2002.1034527","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034527","url":null,"abstract":"In this work it is shown for the first time how to calculate in advance by momentum-based noise simulation for stationary Monte Carlo (MC) device simulations the CPU time, which is necessary to achieve a predefined error level. In addition, analytical expressions for the simulation-time factor of terminal current estimation are given. Without further improvements of the MC algorithm MC simulations of small terminal currents are found to be often prohibitively CPU intensive.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131311616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Finite element analysis of stress evolution in Si based front and back ends micro structures 硅基前后端微结构应力演化的有限元分析
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034565
V. Senez, A. Armigliato, G. Carlotti, G. Carnevale, H. Jaouen, I. de Wolff
{"title":"Finite element analysis of stress evolution in Si based front and back ends micro structures","authors":"V. Senez, A. Armigliato, G. Carlotti, G. Carnevale, H. Jaouen, I. de Wolff","doi":"10.1109/SISPAD.2002.1034565","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034565","url":null,"abstract":"Nowadays, silicon technologies with feature sizes around 100 nm are used in the microelectronics industry to produce gigabits integrated circuits. The prime part of numerical simulation in their development is now well established. One of the purpose of the numerical analyses is the improvement of the mechanical reliability. We synthetize in this paper various works we have performed on the macroscopical modeling and simulation of stress problems and their effects in silicon technologies.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131650989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Numerical modeling of silicon film deposition in very-high-frequency plasma reactor 甚高频等离子体反应器中硅膜沉积的数值模拟
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034535
K. Satake, Y. Kobayashi, S. Morita
{"title":"Numerical modeling of silicon film deposition in very-high-frequency plasma reactor","authors":"K. Satake, Y. Kobayashi, S. Morita","doi":"10.1109/SISPAD.2002.1034535","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034535","url":null,"abstract":"We present a numerical modeling of plasma-enhanced chemical vapor deposition (PECVD) of silicon film from SiH/sub 4/ and H/sub 2/ gas mixtures in very-high-frequency (VHF) plasma reactor. The model is composed by electron impact, gas-phase, and surface reactions in a well-mixed reactor model. A set of plasma parameters such as electron density, electron temperature and electron impact reaction rates is determined separately by nonequilibrium plasma model and used as inputs for well-mixed reactor models. The gas-phase reactions include electron impact and neutral-neutral reactions. Some of unknown rates of surface reactions are determined using quantum chemical calculations and transition state theory. In well-mixed reactor models, concentrations of each chemical species are calculated in a steady state condition using mass conservation equation uniformed through the reactor. Numerical results of growth rate as a function of plasma reactor operating parameters show good agreement with experimental ones. Finally optimal operating parameters are investigated using our model combined with design of experiments and optimization techniques.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116159374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A new SP (simultaneous polishing) model for copper CMP process 铜CMP工艺的同步抛光新模型
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034567
T. Ohta, K. Suzuki
{"title":"A new SP (simultaneous polishing) model for copper CMP process","authors":"T. Ohta, K. Suzuki","doi":"10.1109/SISPAD.2002.1034567","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034567","url":null,"abstract":"For the copper damascene process, dummy fill is used to improve over-polishing problems such as dishing and erosion. Dummy placement based on design rules is ordinary used, but to improve the efficiency of the dummy fill, model-based design is necessary So, we have developed a new SP (simultaneous, polishing) model for Cu-CMP and developed a dummy pattern design system to utilize the model. Using the model, simulation results of dishing and erosion well agree with experiments within 10% errors, and calculation time is fast enough for LSI design. The system we develop can be utilized to design dummy placement practically.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"20 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131197920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Surface mobility in silicon at large operating temperature 大工作温度下硅的表面迁移率
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034506
S. Reggiani, A. Valdinoci, L. Colalongo, M. Rudan, G. Baccarani, A. Stricker, F. Illien, N. Felber, W. Fichtner, S. Mettler, S. Lindenkreuz, L. Zullino
{"title":"Surface mobility in silicon at large operating temperature","authors":"S. Reggiani, A. Valdinoci, L. Colalongo, M. Rudan, G. Baccarani, A. Stricker, F. Illien, N. Felber, W. Fichtner, S. Mettler, S. Lindenkreuz, L. Zullino","doi":"10.1109/SISPAD.2002.1034506","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034506","url":null,"abstract":"An experimental investigation on high-temperature carrier mobility in silicon inversion layers is carried out with the aim of improving our understanding of carrier transport at the onset of second breakdown. Special MOSFET structures suitable for Hall measurements were designed and manufactured using the BCD-3 technology available at ST-Microelectronics. Hall measurements were carried out using a special measurement setup that allows operating temperatures in excess of 400/spl deg/C to be reached within the polar expansions of a commercial magnet. A novel extraction methodology allowing for the determination of the Hall factor and the carrier mobility against impurity concentration and lattice temperature was devised. Finally, a compact mobility model suitable for implementation in device simulators has been worked out, implemented in the DESSIS/sup /spl copy// code and validated within an industrial environment.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116506436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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