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2021 IEEE Hot Chips 33 Symposium (HCS)最新文献

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AI Compute Chip from Enflame 来自Enflame的AI计算芯片
2021 IEEE Hot Chips 33 Symposium (HCS) Pub Date : 2021-08-22 DOI: 10.1109/HCS52781.2021.9567224
Ryan Liu, Chuang Feng
{"title":"AI Compute Chip from Enflame","authors":"Ryan Liu, Chuang Feng","doi":"10.1109/HCS52781.2021.9567224","DOIUrl":"https://doi.org/10.1109/HCS52781.2021.9567224","url":null,"abstract":"DTU 1.0 SOC • 32 AI compute core, 4 clusters • 40 Data transfer engines • 4 High speed interconnects • 2 HBM2 providing 512GB/s bandwidth","PeriodicalId":246531,"journal":{"name":"2021 IEEE Hot Chips 33 Symposium (HCS)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126137014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Plug-and-Play Universal Photonic Processor for Quantum Information Processing 即插即用的量子信息处理通用光子处理器
2021 IEEE Hot Chips 33 Symposium (HCS) Pub Date : 2021-08-22 DOI: 10.1109/HCS52781.2021.9566977
C. Taballione
{"title":"A Plug-and-Play Universal Photonic Processor for Quantum Information Processing","authors":"C. Taballione","doi":"10.1109/HCS52781.2021.9566977","DOIUrl":"https://doi.org/10.1109/HCS52781.2021.9566977","url":null,"abstract":"Large-scale and programmable quantum photonic processors are needed to control photonic quantum computations that lead to a quantum advantage. Here, we present a universal 12-mode quantum photonic processor which is the largest of its kind to date. The processor is remotely controllable and seamlessly integrated with a dedicated control software, making the device fully plug-and-play.","PeriodicalId":246531,"journal":{"name":"2021 IEEE Hot Chips 33 Symposium (HCS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122988608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multi-Million Core, Multi-Wafer AI Cluster 百万核、多晶圆AI集群
2021 IEEE Hot Chips 33 Symposium (HCS) Pub Date : 2021-08-22 DOI: 10.1109/HCS52781.2021.9567153
Sean Lie
{"title":"Multi-Million Core, Multi-Wafer AI Cluster","authors":"Sean Lie","doi":"10.1109/HCS52781.2021.9567153","DOIUrl":"https://doi.org/10.1109/HCS52781.2021.9567153","url":null,"abstract":"Building and deploying a new class of computer system Designed for the purpose of accelerating AI and changing the future of AI work","PeriodicalId":246531,"journal":{"name":"2021 IEEE Hot Chips 33 Symposium (HCS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114236133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
World Largest Mobile Image Sensor with All Directional Phase Detection Auto Focus Function 世界上最大的移动图像传感器，具有全方位相位检测自动对焦功能
2021 IEEE Hot Chips 33 Symposium (HCS) Pub Date : 2021-08-22 DOI: 10.1109/HCS52781.2021.9567122
Sukki Yoon, Jungbin Yun, Yunhwan Jung, Ilyun Jeong, Junghee Choi, Wooseok Choi, Jeongguk Lee, Hansoo Lee, Juhyun Ko
{"title":"World Largest Mobile Image Sensor with All Directional Phase Detection Auto Focus Function","authors":"Sukki Yoon, Jungbin Yun, Yunhwan Jung, Ilyun Jeong, Junghee Choi, Wooseok Choi, Jeongguk Lee, Hansoo Lee, Juhyun Ko","doi":"10.1109/HCS52781.2021.9567122","DOIUrl":"https://doi.org/10.1109/HCS52781.2021.9567122","url":null,"abstract":"The world largest mobile image sensor The large Tetra-Cell pixel guarantees DSR-like image with higher SNR in the dark and better resolution in the bright Dual Pixel Pro All directional phase detection auto focus function can improve the AF performance Smart ISO Pro High dynamic range solution without no motion artifact and merging function in AP Staggered HDR Provide cost-effective high dynamic range image without the motion blue The innovative low power scheme Provide the lower analog power consumption on 2.2V supply voltage Flexible high-speed interface MIPI combo can provide the user flexibility with EMI immunity","PeriodicalId":246531,"journal":{"name":"2021 IEEE Hot Chips 33 Symposium (HCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130896668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An Energy-efficient Floating-Point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory 基于内存指数计算异构计算架构的高能效浮点DNN处理器
2021 IEEE Hot Chips 33 Symposium (HCS) Pub Date : 2021-08-22 DOI: 10.1109/HCS52781.2021.9566881
Juhyoung Lee, Jihoon Kim, Wooyoung Jo, Sangyeob Kim, Sangjin Kim, Donghyeon Han, Jinsu Lee, H. Yoo
{"title":"An Energy-efficient Floating-Point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory","authors":"Juhyoung Lee, Jihoon Kim, Wooyoung Jo, Sangyeob Kim, Sangjin Kim, Donghyeon Han, Jinsu Lee, H. Yoo","doi":"10.1109/HCS52781.2021.9566881","DOIUrl":"https://doi.org/10.1109/HCS52781.2021.9566881","url":null,"abstract":"Abstract of Proposed FP CIM Processor (1) Heterogeneous FP Computing Arch. : Separate optimization of FP computing: Realize 2 cycles FP MAC w/ CIM (2) Exponent Computing-in-Memory: In-memory AND/NOR + BL charge reusing: Total memory power 46.4% 2) Mantissa Free Exponent Calculation: Removing redundant normalization: Total MAC power 14.4%","PeriodicalId":246531,"journal":{"name":"2021 IEEE Hot Chips 33 Symposium (HCS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125388769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Xilinx Edge Processors 赛灵思边缘处理器
2021 IEEE Hot Chips 33 Symposium (HCS) Pub Date : 2021-08-22 DOI: 10.1109/HCS52781.2021.9567521
Ross Freeman, James V. Barnett, Bernard V. Vonderschmitt
{"title":"Xilinx Edge Processors","authors":"Ross Freeman, James V. Barnett, Bernard V. Vonderschmitt","doi":"10.1109/HCS52781.2021.9567521","DOIUrl":"https://doi.org/10.1109/HCS52781.2021.9567521","url":null,"abstract":"ADAPTABLE TO MULTIPLE WORKLOADS • Versal AI Core • Versal Premium • Versal AI Edge COMPUTE ACCELERATION • Scalar Engines • Adaptable Engines • Intelligent Engines PLATFORM • Software programmable NoC • Platform Management Controller • Dedicated Interfaces (e.g., PCIe, DDR)","PeriodicalId":246531,"journal":{"name":"2021 IEEE Hot Chips 33 Symposium (HCS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123004777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Mozart: Designing for Software Maturity and the Next Paradigm for Chip Architectures 莫扎特:软件成熟度设计和芯片架构的下一个范例
2021 IEEE Hot Chips 33 Symposium (HCS) Pub Date : 2021-08-22 DOI: 10.1109/HCS52781.2021.9567306
K. Sankaralingam, Tony Nowatzki, G. Wright, Poly Palamuttam, Jitu Khare, Vinay Gangadhar, Preyas Shah
{"title":"Mozart: Designing for Software Maturity and the Next Paradigm for Chip Architectures","authors":"K. Sankaralingam, Tony Nowatzki, G. Wright, Poly Palamuttam, Jitu Khare, Vinay Gangadhar, Preyas Shah","doi":"10.1109/HCS52781.2021.9567306","DOIUrl":"https://doi.org/10.1109/HCS52781.2021.9567306","url":null,"abstract":"Where does AI hardware/software stand today? 1. The computational diversity needed to support AI is increasing2. The software user experience expectations is increasing3. GPU software maturity* is unrivalled in completeness and hence allows near complete dominance among AI industry deployment and researchers.4. This support for model diversity is fuelling these trends and increasing GPU adoption!* NVIDIA DL stack - cuDNN, TensorRT, etc.","PeriodicalId":246531,"journal":{"name":"2021 IEEE Hot Chips 33 Symposium (HCS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122218977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
SambaNova SN10 RDU:Accelerating Software 2.0 with Dataflow SambaNova SN10 RDU:使用数据流加速软件2.0
2021 IEEE Hot Chips 33 Symposium (HCS) Pub Date : 2021-08-22 DOI: 10.1109/HCS52781.2021.9567250
R. Prabhakar, Sumti Jairath
{"title":"SambaNova SN10 RDU:Accelerating Software 2.0 with Dataflow","authors":"R. Prabhakar, Sumti Jairath","doi":"10.1109/HCS52781.2021.9567250","DOIUrl":"https://doi.org/10.1109/HCS52781.2021.9567250","url":null,"abstract":"The following is intended to outline our general product direction at this time. There is no obligation to update this presentation and the Company’s products and direction are always subject to change. This presentation is intended for information purposes only and may not be relied upon for any purchasing, partnership, or other decisions.","PeriodicalId":246531,"journal":{"name":"2021 IEEE Hot Chips 33 Symposium (HCS)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116108927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Next Generation “Zen 3” Core 下一代“禅宗3”核心
2021 IEEE Hot Chips 33 Symposium (HCS) Pub Date : 2021-08-22 DOI: 10.1109/HCS52781.2021.9567108
Mark Evers, L. Barnes, Mike Clark
{"title":"Next Generation “Zen 3” Core","authors":"Mark Evers, L. Barnes, Mike Clark","doi":"10.1109/HCS52781.2021.9567108","DOIUrl":"https://doi.org/10.1109/HCS52781.2021.9567108","url":null,"abstract":"This presentation contains forward-looking statements concerning Advanced Micro Devices, Inc. (AMD) including, but not limited to, the features, functionality, availability, timing, expectations and expected benefits of AMD future products, including Ryzen™ 5000 Series CPUs and Socket AM4, which are made pursuant to the Safe Harbor provisions of the Private Securities Litigation Reform Act of 1995. Forward-looking statements are commonly identified by words such as “would,” “may,” “expects,” “believes,” “plans,” “intends,” “projects” and other terms with similar meaning. Investors are cautioned that the forward-looking statements in this presentation are based on current beliefs, assumptions and expectations, speak only as of the date of this presentation and involve risks and uncertainties that could cause actual results to differ materially from current expectations. Such statements are subject to certain known and unknown risks and uncertainties, many of which are difficult to predict and generally beyond AMD’s control, that could cause actual results and other future events to differ materially from those expressed in, or implied or projected by, the forward-looking information and statements. Investors are urged to review in detail the risks and uncertainties in AMD’s Securities and Exchange Commission filings, including but not limited to AMD’s Quarterly Report on Form 10-Qfrom the quarter ending on June 26, 2021.","PeriodicalId":246531,"journal":{"name":"2021 IEEE Hot Chips 33 Symposium (HCS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114683344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A CORDIC-based Trigonometric Hardware Accelerator with Custom Instruction in 32-bit RISC-V System-on-Chip 基于cordic的32位RISC-V片上系统自定义指令三角硬件加速器
2021 IEEE Hot Chips 33 Symposium (HCS) Pub Date : 2021-08-22 DOI: 10.1109/HCS52781.2021.9567158
Khai-Duy Nguyen, Tuan-Kiet Dang, Trong-Thuc Hoang, Q. N. Q. Nhu, C. Pham
{"title":"A CORDIC-based Trigonometric Hardware Accelerator with Custom Instruction in 32-bit RISC-V System-on-Chip","authors":"Khai-Duy Nguyen, Tuan-Kiet Dang, Trong-Thuc Hoang, Q. N. Q. Nhu, C. Pham","doi":"10.1109/HCS52781.2021.9567158","DOIUrl":"https://doi.org/10.1109/HCS52781.2021.9567158","url":null,"abstract":"This poster presents a 32-bit Reduced Instruction Set Computer five (RISC-V) microprocessor with a COordinate Rotation DIgital Computer (CORDIC) algorithm accelerator. The implemented core processor is the VexRiscv CPU, an RV32IM variant of the RISC-V ISA processor. Within the VexRiscv core, the CORDIC accelerator was connected directly to the Execute stage. The core was placed in Briey System-on-Chip (SoC) and was synthesized on Field Programmable Gate Array (FPGA) and on Application Specific Integrated Chip (ASIC) level with the cell logic of ROHM- 180nm technology","PeriodicalId":246531,"journal":{"name":"2021 IEEE Hot Chips 33 Symposium (HCS)","volume":"400 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124453004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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