Khai-Duy Nguyen, Tuan-Kiet Dang, Trong-Thuc Hoang, Q. N. Q. Nhu, C. Pham
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A CORDIC-based Trigonometric Hardware Accelerator with Custom Instruction in 32-bit RISC-V System-on-Chip
This poster presents a 32-bit Reduced Instruction Set Computer five (RISC-V) microprocessor with a COordinate Rotation DIgital Computer (CORDIC) algorithm accelerator. The implemented core processor is the VexRiscv CPU, an RV32IM variant of the RISC-V ISA processor. Within the VexRiscv core, the CORDIC accelerator was connected directly to the Execute stage. The core was placed in Briey System-on-Chip (SoC) and was synthesized on Field Programmable Gate Array (FPGA) and on Application Specific Integrated Chip (ASIC) level with the cell logic of ROHM- 180nm technology
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