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2021 IEEE Hot Chips 33 Symposium (HCS)最新文献

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Arm Neoverse N2: Arm’s 2nd generation high performance infrastructure CPUs and system IPs Arm Neoverse N2: Arm第二代高性能基础架构cpu和系统ip
2021 IEEE Hot Chips 33 Symposium (HCS) Pub Date : 2021-08-22 DOI: 10.1109/HCS52781.2021.9567483
Andrea Pellegrini
{"title":"Arm Neoverse N2: Arm’s 2nd generation high performance infrastructure CPUs and system IPs","authors":"Andrea Pellegrini","doi":"10.1109/HCS52781.2021.9567483","DOIUrl":"https://doi.org/10.1109/HCS52781.2021.9567483","url":null,"abstract":"This benchmark presentation made by Arm Ltd and its subsidiaries (Arm) contains forward-looking statements and information. The information contained herein is therefore provided by Arm on an “as-is“ basis without warranty or liability of any kind. While Arm has made every attempt to ensure that the information contained in the benchmark presentation is accurate and reliable at the time of its publication, it cannot accept responsibility for any errors, omissions or inaccuracies or for the results obtained from the use of such information and should be used for guidance purposes only and is not intended to replace discussions with a duly appointed representative of Arm. Any results or comparisons shown are for general information purposes only and any particular data or analysis should not be interpreted as demonstrating a cause and effect relationship. Comparable performance on any performance indicator does not guarantee comparable performance on any other performance indicator.","PeriodicalId":246531,"journal":{"name":"2021 IEEE Hot Chips 33 Symposium (HCS)","volume":"686 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122977633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner 基于4位笛卡尔积MAC阵列和流水线激活对齐器的深度随机稀疏神经网络边缘推理引擎
2021 IEEE Hot Chips 33 Symposium (HCS) Pub Date : 2021-08-22 DOI: 10.1109/HCS52781.2021.9567328
Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, M. Motomura
{"title":"Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner","authors":"Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, M. Motomura","doi":"10.1109/HCS52781.2021.9567328","DOIUrl":"https://doi.org/10.1109/HCS52781.2021.9567328","url":null,"abstract":"A 4b-quantized convolutional neural network (CNN) inference engine for edge-AI is presented featuring a Cartesian-product MAC array and pipelined activation aligners targeting deep-/random-pruned models. A 40nm prototype with 32x32 MACs and 5Mb SRAM runs at 534 MHz, 1.07 TOPS, 352 mW at 1.1V, and attains 5.30 dense TOPS/W, 234 MHz at 0.8V. Sparse TOPS/W reaches 26.5 when running a randomly pruned model (after 88% pruning). Training algorithms for obtaining highly efficient sparse/quantized models are also proposed.","PeriodicalId":246531,"journal":{"name":"2021 IEEE Hot Chips 33 Symposium (HCS)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129796048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Morpheus II: A RISC-V Security Extension for Protecting Vulnerable Software and Hardware Morpheus II: RISC-V安全扩展，用于保护易受攻击的软件和硬件
2021 IEEE Hot Chips 33 Symposium (HCS) Pub Date : 2021-08-22 DOI: 10.1109/HCS52781.2021.9567000
T. Austin, Austin Harris, Tarunesh Verma, Shijia Wei, Alex Kisil, Misiker Tadesse Aga, V. Bertacco, Baris Kasikci, Mohit Tiwari
{"title":"Morpheus II: A RISC-V Security Extension for Protecting Vulnerable Software and Hardware","authors":"T. Austin, Austin Harris, Tarunesh Verma, Shijia Wei, Alex Kisil, Misiker Tadesse Aga, V. Bertacco, Baris Kasikci, Mohit Tiwari","doi":"10.1109/HCS52781.2021.9567000","DOIUrl":"https://doi.org/10.1109/HCS52781.2021.9567000","url":null,"abstract":"• Software protects data • All software is (eventually) hackable • Finding/fixing vulnerabilities doesn’t scale • E.g., Malicious 7: buffer errors, code injection, numeric errors, permissions, resource mgt","PeriodicalId":246531,"journal":{"name":"2021 IEEE Hot Chips 33 Symposium (HCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125246803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
ENIAD: A Reconfigurable Near-data Processing Architecture for Web-Scale AI-enriched Big Data Service ENIAD:面向web级ai大数据服务的可重构近数据处理架构
2021 IEEE Hot Chips 33 Symposium (HCS) Pub Date : 2021-08-22 DOI: 10.1109/HCS52781.2021.9567229
Jialiang Zhang, JingJane Li
{"title":"ENIAD: A Reconfigurable Near-data Processing Architecture for Web-Scale AI-enriched Big Data Service","authors":"Jialiang Zhang, JingJane Li","doi":"10.1109/HCS52781.2021.9567229","DOIUrl":"https://doi.org/10.1109/HCS52781.2021.9567229","url":null,"abstract":"To meet the surging demands required by AI-enriched Big Data services, cloud vendors are turning toward domain specific accelerators for improved efficiency, scalability and performance. ENIAD, the first end-to-end infrastructure for AI-enriched Big Data serving in real time, accelerates both deep neural network inferencing and billion-scale indexing at the data-center scale. Exploiting near- data computation, reconfigurable computing and rapid/agile hardware deployment flow, ENIAD serves state-of-the-art, online built indexing service with high efficiency at low batch sizes. A high-performance, index (data)-adaptable FPGA soft processor is at the heart of the system and able to serve 10x larger index size with 14x lower latency compared to state-of-the-art CPU and GPU architectures.","PeriodicalId":246531,"journal":{"name":"2021 IEEE Hot Chips 33 Symposium (HCS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121809756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Qualcomm® Cloud Al 100 : 12TOPS/W Scalable, High Performance and Low Latency Deep Learning Inference Accelerator 高通®Cloud Al 100: 12TOPS/W可扩展，高性能和低延迟深度学习推理加速器
2021 IEEE Hot Chips 33 Symposium (HCS) Pub Date : 2021-08-22 DOI: 10.1109/HCS52781.2021.9567417
K. Chatha
{"title":"Qualcomm® Cloud Al 100 : 12TOPS/W Scalable, High Performance and Low Latency Deep Learning Inference Accelerator","authors":"K. Chatha","doi":"10.1109/HCS52781.2021.9567417","DOIUrl":"https://doi.org/10.1109/HCS52781.2021.9567417","url":null,"abstract":"Future of Al in Data Center Demands Breakthrough Technology Compute power not keeping up with business needs to deliver best in class services Al Ubiquitous in Data Center, • Al fundamental, for next gen business analytics for bestcustomer experience and insights • Velocity of insight key to business leadership","PeriodicalId":246531,"journal":{"name":"2021 IEEE Hot Chips 33 Symposium (HCS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133257109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
LightOn Optical Processing Unit : Scaling-up AI and HPC with a Non von Neumann co-processor LightOn光处理单元:用非冯·诺伊曼协处理器扩展AI和HPC
2021 IEEE Hot Chips 33 Symposium (HCS) Pub Date : 2021-07-25 DOI: 10.1109/HCS52781.2021.9567166
C. Brossollet, Alessandro Cappelli, I. Carron, Charidimos Chaintoutis, A. Chatelain, L. Daudet, S. Gigan, Daniel Hesslow, F. Krzakala, Julien Launay, Safa Mokaadi, F. Moreau, Kilian Muller, Ruben Ohana, Gustave Pariente, Iacopo Poli, G. L. Tommasone
{"title":"LightOn Optical Processing Unit : Scaling-up AI and HPC with a Non von Neumann co-processor","authors":"C. Brossollet, Alessandro Cappelli, I. Carron, Charidimos Chaintoutis, A. Chatelain, L. Daudet, S. Gigan, Daniel Hesslow, F. Krzakala, Julien Launay, Safa Mokaadi, F. Moreau, Kilian Muller, Ruben Ohana, Gustave Pariente, Iacopo Poli, G. L. Tommasone","doi":"10.1109/HCS52781.2021.9567166","DOIUrl":"https://doi.org/10.1109/HCS52781.2021.9567166","url":null,"abstract":"Beyond pure Von Neumann processing Scalability of AI / HPC models is limited by the Von Neumann bottleneck for accessing massive amounts of memory, driving up power consumption.","PeriodicalId":246531,"journal":{"name":"2021 IEEE Hot Chips 33 Symposium (HCS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131503276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Photonic co-processors in HPC: Using LightOn OPUs for Randomized Numerical Linear Algebra 高性能计算中的光子协处理器:在随机数值线性代数中使用LightOn opu
2021 IEEE Hot Chips 33 Symposium (HCS) Pub Date : 2021-04-29 DOI: 10.1109/HCS52781.2021.9566948
Daniel Hesslow, Alessandro Cappelli, I. Carron, L. Daudet, Raphael Lafargue, Kilian Muller, Ruben Ohana, Gustave Pariente, Iacopo Poli
{"title":"Photonic co-processors in HPC: Using LightOn OPUs for Randomized Numerical Linear Algebra","authors":"Daniel Hesslow, Alessandro Cappelli, I. Carron, L. Daudet, Raphael Lafargue, Kilian Muller, Ruben Ohana, Gustave Pariente, Iacopo Poli","doi":"10.1109/HCS52781.2021.9566948","DOIUrl":"https://doi.org/10.1109/HCS52781.2021.9566948","url":null,"abstract":"Exact computation of linear algebra operations is challenging or even impossible at extreme scale By leveraging randomization we can get approximate results at reduced computational cost Lighton OPU: The first commercially available photonic Co-Processor","PeriodicalId":246531,"journal":{"name":"2021 IEEE Hot Chips 33 Symposium (HCS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114289319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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