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2022 IEEE Design Methodologies Conference (DMC)最新文献

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Towards Real Time Thermal Simulations for Design Optimization using Graph Neural Networks 面向设计优化的实时热仿真图神经网络
2022 IEEE Design Methodologies Conference (DMC) Pub Date : 2022-09-01 DOI: 10.1109/DMC55175.2022.9906469
H. Sanchis-Alepuz, Monika Stipsitz
{"title":"Towards Real Time Thermal Simulations for Design Optimization using Graph Neural Networks","authors":"H. Sanchis-Alepuz, Monika Stipsitz","doi":"10.1109/DMC55175.2022.9906469","DOIUrl":"https://doi.org/10.1109/DMC55175.2022.9906469","url":null,"abstract":"This paper presents a method to simulate the thermal behavior of 3D systems using a graph neural network. The method discussed achieves a significant speed-up with respect to a traditional finite-element simulation. The graph neural network is trained on a diverse dataset of 3D CAD designs and the corresponding finite-element simulations, representative of the different geometries, material properties and losses that appear in the design of electronic systems. We present for the transient thermal behavior of a test system. The accuracy of the network result for one-step predictions is remarkable (0.003% error). After 400 time steps, the accumulated error reaches 0.78 %. The computing time of each time step is 50 ms. Reducing the accumulated error is the current focus of our work. In the future, a tool such as the one we are presenting could provide nearly instantaneous approximations of the thermal behavior of a system that can be used for design optimization.","PeriodicalId":245908,"journal":{"name":"2022 IEEE Design Methodologies Conference (DMC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134628044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Implementation of Multi-Expansion Point Model Order Reduction for Coupled PEEC-Semiconductor Simulations 耦合peec -半导体仿真中多扩展点模型降阶的实现
2022 IEEE Design Methodologies Conference (DMC) Pub Date : 2022-09-01 DOI: 10.1109/DMC55175.2022.9906539
V. Blakaj, Bawar Jalal, Paul L. Evans
{"title":"Implementation of Multi-Expansion Point Model Order Reduction for Coupled PEEC-Semiconductor Simulations","authors":"V. Blakaj, Bawar Jalal, Paul L. Evans","doi":"10.1109/DMC55175.2022.9906539","DOIUrl":"https://doi.org/10.1109/DMC55175.2022.9906539","url":null,"abstract":"An algorithm for the generation of reduced order PEEC models is presented, this algorithm addresses the additional complexity resulting from use of multiple expansion points. Nested iterative solvers for the L and P PEEC sub-matrices are used and these solvers are accelerated using multipole expansions. The reduced order models are validated in the frequency domain against commercial finite element software, and time-domain co-simulation with accurate semiconductor models is then demonstrated. It is shown that a coupled, 3D PCB mounted inductor and semiconductor co-simulation with 100,000 time-steps can be completed in 23 minutes including reduced order model generation.","PeriodicalId":245908,"journal":{"name":"2022 IEEE Design Methodologies Conference (DMC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133692599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Thermal Runaway Mitigation through Electrothermal Constraints Mapping for MCPM Layout Optimization 基于电热约束映射的MCPM布局优化热失控缓解
2022 IEEE Design Methodologies Conference (DMC) Pub Date : 2022-09-01 DOI: 10.1109/DMC55175.2022.9906468
Quang Le, M. Hossain, Tristan M. Evans, Yarui Peng, H. Mantooth
{"title":"Thermal Runaway Mitigation through Electrothermal Constraints Mapping for MCPM Layout Optimization","authors":"Quang Le, M. Hossain, Tristan M. Evans, Yarui Peng, H. Mantooth","doi":"10.1109/DMC55175.2022.9906468","DOIUrl":"https://doi.org/10.1109/DMC55175.2022.9906468","url":null,"abstract":"Along with the developments in power electronic packaging technology, many studies on design automation for MCPMs layout further push the design limits for their power density and compactness. Among these studies, PowerSynth has shown the complete design flow for MCPMs, which offers a multiobjective layout optimization algorithm and reduced-order models for electrical parasitic extraction and thermal evaluation. While these models are accurate, there is no connection between the electrical parasitic and device temperature during the layout optimization process. Hence, the multi-objective optimization algorithm optimizes these objectives separately without insights into their impacts on the reliability and performance of the wide bandgap (WBG) device. This limitation can lead to a layout solution with undesirable performance compared to the WBG device’s safe operation area (SOA). Therefore, this work incorporates the WBG physics-based device knowledge into the power loss calculation for a more accurate electro-thermal prediction in PowerSynth. A better decision can then be made on the most suitable thermal management system.","PeriodicalId":245908,"journal":{"name":"2022 IEEE Design Methodologies Conference (DMC)","volume":"357 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133168675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Device-Centric Firmware Malware Detection for Smart Inverters using Deep Transfer Learning 使用深度迁移学习的智能逆变器以设备为中心的固件恶意软件检测
2022 IEEE Design Methodologies Conference (DMC) Pub Date : 2022-09-01 DOI: 10.1109/DMC55175.2022.9906538
Syed. R. B. Alvee, Bohyun Ahn, Seerin Ahmad, Kyoung-Tak Kim, Taesic Kim, Jianwu Zeng
{"title":"Device-Centric Firmware Malware Detection for Smart Inverters using Deep Transfer Learning","authors":"Syed. R. B. Alvee, Bohyun Ahn, Seerin Ahmad, Kyoung-Tak Kim, Taesic Kim, Jianwu Zeng","doi":"10.1109/DMC55175.2022.9906538","DOIUrl":"https://doi.org/10.1109/DMC55175.2022.9906538","url":null,"abstract":"Since future power grids are inverter-dominant grids and inverters are getting smarter by incorporating remote access and seamless firmware update, it is anticipated that malware attackers will directly target smart inverters. However, malware threats targeting smart inverters have been less studied yet. This paper explores potential malware attacks targeting smart inverters and proposes a deep transfer-learning (DTL)-based malware detection framework for smart inverters. The proposed DTL method can significantly reduce development time and efforts for an artificial intelligence-based malware detection algorithm while improving detection accuracy. The experimental result shows that the proposed method achieves 98% of firmware malware detection accuracy. This approach will be transformative to other smart grid devices enabling seamless firmware update.","PeriodicalId":245908,"journal":{"name":"2022 IEEE Design Methodologies Conference (DMC)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129148873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Digital Twin of an ANPC inverter with integrated Design-For-Trust 集成信任设计的ANPC逆变器的数字孪生
2022 IEEE Design Methodologies Conference (DMC) Pub Date : 2022-09-01 DOI: 10.1109/DMC55175.2022.9906472
Paulo Custódio, Brady J. Mcbride, Thao Le, Justin Jackson, Kelby Haulmark, J. Di, C. Farnell, H. Mantooth
{"title":"Digital Twin of an ANPC inverter with integrated Design-For-Trust","authors":"Paulo Custódio, Brady J. Mcbride, Thao Le, Justin Jackson, Kelby Haulmark, J. Di, C. Farnell, H. Mantooth","doi":"10.1109/DMC55175.2022.9906472","DOIUrl":"https://doi.org/10.1109/DMC55175.2022.9906472","url":null,"abstract":"Reducing costs and increasing manufacturing output while creating reliable products are three essential components needed to keep a business competitive. In the past, having an asset that could address these three challenges at the same time would be challeging. However, recent advances in computer processing capabilities coupled with increases to network speeds allowed such a system to become possible; and this is known as a Digital Twin (DT), which represents a virtual copy of a production system or a product. This work exhibits a DT application of an Active Neutral Point Clamped (ANPC) inverter using a controller. The controller emulates the ANPC responses of a new Digital Signal Processing (DSP) firmware and validates this new firmware by using Design-For-Trust (DFTr) characteristics. If the new firmware is malicious, then it should be rejected, thus adding preemptive protection measures for inverter based distributed energy resources.","PeriodicalId":245908,"journal":{"name":"2022 IEEE Design Methodologies Conference (DMC)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122725305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Computer-Aided Thermal Analysis of an Electric-Vehicle Universal Battery Supercharger 电动汽车通用电池增压器的计算机辅助热分析
2022 IEEE Design Methodologies Conference (DMC) Pub Date : 2022-09-01 DOI: 10.1109/DMC55175.2022.9906540
Anik Niraj Desai, S. Mazumder, Nikhil Kumar
{"title":"Computer-Aided Thermal Analysis of an Electric-Vehicle Universal Battery Supercharger","authors":"Anik Niraj Desai, S. Mazumder, Nikhil Kumar","doi":"10.1109/DMC55175.2022.9906540","DOIUrl":"https://doi.org/10.1109/DMC55175.2022.9906540","url":null,"abstract":"The goal of this work is to realize an effective design of a cold plate to manage the device thermal load of an electric-vehicle (EV) universal battery supercharger (UBS). The cold-plate design ensures reduced peak temperatures of the semiconductor dies and the modules and temperature variation among the modules thereby reducing the device losses. Our work initiated with the design of a computer-aided-design (CAD) model for a 60-kW SiC UBS. The thermal analysis was conducted using Thermal and Fluent packages of ANSYS. After the modeling, a fin-based cold-plate design was carried out for localized cooling of SiC modules. Subsequently, several cold-plate geometries were pursued eventually finalizing one design that yielded the most effective cooling.","PeriodicalId":245908,"journal":{"name":"2022 IEEE Design Methodologies Conference (DMC)","volume":"177 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124745749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Simulating the Conducted EM Emissions of a Synchronous Buck Converter using an 80V GaN Half Bridge Power Stage 用80V GaN半桥功率级模拟同步降压变换器的传导电磁发射
2022 IEEE Design Methodologies Conference (DMC) Pub Date : 2022-09-01 DOI: 10.1109/DMC55175.2022.9906543
S. Muff, L. Eichinger, H. Barnes
{"title":"Simulating the Conducted EM Emissions of a Synchronous Buck Converter using an 80V GaN Half Bridge Power Stage","authors":"S. Muff, L. Eichinger, H. Barnes","doi":"10.1109/DMC55175.2022.9906543","DOIUrl":"https://doi.org/10.1109/DMC55175.2022.9906543","url":null,"abstract":"A recently published paper [1] on the analytical modeling of the conducted EM Emissions of a synchronous Buck converter for different voltage ratios demonstrates a behavioral model to predict the emitted spectrum for GaN and SiC based buck converters. The results show reasonable agreement between analytical predicted and measured conducted EM spectrum. This presentation shows an alternative methodology focusing on the layout implementation of the converter stage based on a commercially available EM extraction tool. This solution benefits from a respective switch model included in the software, offering a fast representation of the switching behavior without the need of using SPICE models for the switching devices. The results indicate that this methodology enables accurate prediction of the conducted EM spectrum on a virtual level, offering a deeper insight into the parasitic effects of the layout and can reduce the number of hardware iteration cycles.","PeriodicalId":245908,"journal":{"name":"2022 IEEE Design Methodologies Conference (DMC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125447498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Magnetic material modelling using the PEEC method and linear basis functions 利用PEEC方法和线性基函数对磁性材料进行建模
2022 IEEE Design Methodologies Conference (DMC) Pub Date : 2022-09-01 DOI: 10.1109/DMC55175.2022.9906541
V. Blakaj, Bawar Jalal, Paul L. Evans
{"title":"Magnetic material modelling using the PEEC method and linear basis functions","authors":"V. Blakaj, Bawar Jalal, Paul L. Evans","doi":"10.1109/DMC55175.2022.9906541","DOIUrl":"https://doi.org/10.1109/DMC55175.2022.9906541","url":null,"abstract":"The PEEC method has been extensively used to model electromagnetic problems in power electronic systems. It is commonly used for modelling electrical parasitics (e.g. inductance) in busbars but less widely used to model magnetic components (e.g. transformers/inductors). Although an extension of PEEC method exists to include magnetic and dielectric materials, less is published on its use for modelling high permeability magnetic cores with small or no airgap. This case is extremely difficult to accurately model due to the increasing condition number of the magnetic coupling matrix. In this work we demonstrate the difficulty of applying standard PEEC method to typical high permeability magnetic cores and evaluate a modified PEEC method which partially overcomes this problem by increasing the order of the basis functions used to approximate magnetic fields within mesh cells.","PeriodicalId":245908,"journal":{"name":"2022 IEEE Design Methodologies Conference (DMC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129736409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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