Implementation of Multi-Expansion Point Model Order Reduction for Coupled PEEC-Semiconductor Simulations

An algorithm for the generation of reduced order PEEC models is presented, this algorithm addresses the additional complexity resulting from use of multiple expansion points. Nested iterative solvers for the L and P PEEC sub-matrices are used and these solvers are accelerated using multipole expansions. The reduced order models are validated in the frequency domain against commercial finite element software, and time-domain co-simulation with accurate semiconductor models is then demonstrated. It is shown that a coupled, 3D PCB mounted inductor and semiconductor co-simulation with 100,000 time-steps can be completed in 23 minutes including reduced order model generation.