2018 18th International Conference on Application of Concurrency to System Design (ACSD)最新文献_第2页

SOUPS: A Variable Ordering Metric for the Saturation Algorithm SOUPS:饱和算法的可变排序度量

2018 18th International Conference on Application of Concurrency to System Design (ACSD) Pub Date : 2018-06-01 DOI: 10.1109/ACSD.2018.000-4

Benjamin Smith, G. Ciardo

{"title":"SOUPS: A Variable Ordering Metric for the Saturation Algorithm","authors":"Benjamin Smith, G. Ciardo","doi":"10.1109/ACSD.2018.000-4","DOIUrl":"https://doi.org/10.1109/ACSD.2018.000-4","url":null,"abstract":"Multivalued decision diagrams are an excellent technique to study the behavior of discrete-state systems such as Petri nets, but their variable order (mapping places to MDD levels) greatly affects efficiency, and finding an optimal order even just to encode a given set is NP-hard. In state-space generation, the situation is even worse, since the set of markings to be encoded keeps evolving and is known only at the end. Previous heuristics to improve the efficiency of the saturation algorithm often used in state-space generation seek a variable order minimizing a simple function of the Petri net, such as the sum over each transition of the top variable position (SOT) or variable span (SOS). This, too, is NP-hard, so we cannot compute orders that minimize SOT or SOS in most cases but, even if we could, it would have limited effectiveness. For example, SOT and SOS can be led astray by multiple copies of a transition (giving more weight to it), or transitions with equal inputs and outputs (giving weight to transitions that should be ignored). These anomalies inspired us to define SOUPS, a new heuristic that only takes into account the unique and productive portion of each transition. The SOUPS metric can be easily computed, allowing us to use it in standard search techniques like simulated annealing to find good orders. Experiments show that SOUPS is a much better proxy for the quantities we really hope to improve, the memory and time for MDD manipulation during state-space generation.","PeriodicalId":242721,"journal":{"name":"2018 18th International Conference on Application of Concurrency to System Design (ACSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130559191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Partial-Order Reduction for Performance Analysis of Max-Plus Timed Systems 最大+定时系统性能分析的偏阶约简

2018 18th International Conference on Application of Concurrency to System Design (ACSD) Pub Date : 2018-06-01 DOI: 10.1109/ACSD.2018.00007

Bram van der Sanden, M. Geilen, M. Reniers, T. Basten

{"title":"Partial-Order Reduction for Performance Analysis of Max-Plus Timed Systems","authors":"Bram van der Sanden, M. Geilen, M. Reniers, T. Basten","doi":"10.1109/ACSD.2018.00007","DOIUrl":"https://doi.org/10.1109/ACSD.2018.00007","url":null,"abstract":"This paper presents a partial-order reduction method for performance analysis of max-plus timed systems. A max-plus timed system is a network of automata, where the timing behavior of deterministic system tasks (events in an automaton) is captured in (max, +) matrices. These tasks can be characterized in various formalisms like synchronous data flow, Petri nets, or real-time calculus. The timing behavior of the system is captured in a (max, +) state space, calculated from the composition of the automata. This state space may exhibit redundant interleaving with respect to performance aspects like throughput or latency. The goal of this work is to obtain a smaller state space to speed up performance analysis. To achieve this, we first formalize state-space equivalence with respect to throughput and latency analysis. Then, we present a way to compute a reduced composition directly from the specification. This yields a smaller equivalent state space. We perform the reduction on-the-fly, without first computing the full composition. Experiments show the effectiveness of the method on a set of realistic manufacturing system models.","PeriodicalId":242721,"journal":{"name":"2018 18th International Conference on Application of Concurrency to System Design (ACSD)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130967754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Complexity of Reachability for Data-Aware Dynamic Systems 数据感知动态系统可达性的复杂性

2018 18th International Conference on Application of Concurrency to System Design (ACSD) Pub Date : 2018-06-01 DOI: 10.1109/ACSD.2018.000-3

P. Abdulla, C. Aiswarya, M. Atig, M. Montali, Othmane Rezine

引用次数: 5

On Memory Optimal Code Generation for Exposed Datapath Architectures with Buffered Processing Units 带缓冲处理单元的暴露数据路径体系结构的内存最优代码生成

2018 18th International Conference on Application of Concurrency to System Design (ACSD) Pub Date : 2018-06-01 DOI: 10.1109/ACSD.2018.00020

Markus Anders, Anoop Bhagyanath, K. Schneider

{"title":"On Memory Optimal Code Generation for Exposed Datapath Architectures with Buffered Processing Units","authors":"Markus Anders, Anoop Bhagyanath, K. Schneider","doi":"10.1109/ACSD.2018.00020","DOIUrl":"https://doi.org/10.1109/ACSD.2018.00020","url":null,"abstract":"One reason for the limited use of instruction level parallelism (ILP) by conventional processors is their use of registers. Therefore, some recent processor architectures expose their datapaths to the compiler so that the compiler can move values directly between processing units. In particular, the Synchronous Control Asynchronous Dataflow (SCAD) machine is an exposed datapath architecture that uses FIFO buffers at the input and output ports of its processing units. Code generation techniques inspired by classic queue machines can completely eliminate the use of conventional registers in SCAD. However, bounded buffer sizes may still make spill code necessary to store values temporarily in main memory. Since memory access is expensive, it has to be avoided to improve the execution time of programs. Memory optimal code generation problems have been extensively studied in the case of register machines and were proven to be NP-complete. In this paper, we prove that memory optimal code generation for SCAD is also NP-complete by presenting a polynomial-time transformation from memory optimal register code to memory optimal SCAD code. In particular, we present a one to one correspondence between the registers in register machines and the entries of buffers in SCAD machines which indicates that these architectures are closer to each other than expected. Still, SCAD machines offer important advantages: The size of circuit implementations of buffers scales much better compared to register files so that more space is available on SCAD machines with the same chip size. Second, the instruction set of SCAD does not depend on a fixed number of registers or buffers. We therefore present experimental results to compare the execution time of memory optimal SCAD code with FIFO buffers and memory optimal code based on conventional register allocation.","PeriodicalId":242721,"journal":{"name":"2018 18th International Conference on Application of Concurrency to System Design (ACSD)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128308830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Concurrent Secrets with Quantified Suspicion 并行秘密与量化怀疑

2018 18th International Conference on Application of Concurrency to System Design (ACSD) Pub Date : 2018-06-01 DOI: 10.1109/ACSD.2018.00011

L. Hélouët, H. Marchand, J. Mullins

{"title":"Concurrent Secrets with Quantified Suspicion","authors":"L. Hélouët, H. Marchand, J. Mullins","doi":"10.1109/ACSD.2018.00011","DOIUrl":"https://doi.org/10.1109/ACSD.2018.00011","url":null,"abstract":"A system satisfies opacity if its secret behaviors cannot be detected by any user of the system. Opacity of distributed systems was originally set as a boolean predicate before being quantified as measures in a probabilistic setting. This paper considers a different quantitative approach that measures the efforts that a malicious user has to make to detect a secret. This effort is measured as a distance w.r.t a regular profile specifying a normal behavior. This leads to several notions of quantitative opacity. When attackers are passive that is, when they just observe the system, quantitative opacity is brought back to a language inclusion problem, and is PSPACE-complete. When attackers are active, that is, interact with the system in order to detect secret behaviors within a finite depth observation, quantitative opacity turns to be a two-player finite-state quantitative game of partial observation. A winning strategy for an attacker is a sequence of interactions with the system leading to a secret detection without exceeding some profile deviation measure threshold. In this active setting, the complexity of opacity is EXPTIME-complete.","PeriodicalId":242721,"journal":{"name":"2018 18th International Conference on Application of Concurrency to System Design (ACSD)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115475555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

ACSD 2018 Conference Organizers ACSD 2018会议组织者

2018 18th International Conference on Application of Concurrency to System Design (ACSD) Pub Date : 2018-06-01 DOI: 10.1109/acsd.2018.00006

引用次数: 0

[Publisher's information] (发布者的信息)

2018 18th International Conference on Application of Concurrency to System Design (ACSD) Pub Date : 2018-06-01 DOI: 10.1109/acsd.2018.00022

引用次数: 0

Ensuring Consistency between Cycle-Accurate and Instruction Set Simulators 确保周期精确和指令集模拟器之间的一致性

2018 18th International Conference on Application of Concurrency to System Design (ACSD) Pub Date : 2018-06-01 DOI: 10.1109/ACSD.2018.00019

F. Jebali, D. Potop-Butucaru

{"title":"Ensuring Consistency between Cycle-Accurate and Instruction Set Simulators","authors":"F. Jebali, D. Potop-Butucaru","doi":"10.1109/ACSD.2018.00019","DOIUrl":"https://doi.org/10.1109/ACSD.2018.00019","url":null,"abstract":"The xMAS micro-architecture modeling language has been introduced by Intel to facilitate the formal representation and analysis of on-chip interconnect fabrics. In this paper, we introduce xMAStime, a new domain-specific language inspired by xMAS. xMAStime allows the modeling of full micro-architectures comprising certain classes of CPU pipelines, caches, and RAM. Given an in-order pipeline model in xMAStime, we automatically generate both a Cycle-Accurate, Bit-Accurate (CABA) hardware simulator and a timed instruction set simulator where time is accounted with safe upper bounds, as in the pipeline analysis step of Worst-Case Execution Time (WCET) analysis. The approach relies on the theory of endochronous systems, which allows us to ensure functional equivalence and timing consistency between the two generated simulators, using a delay-insensitivity argument. xMAStime is implemented over Lucid Synchrone – a dataflow synchronous language featuring a higher order type system and type inference, which facilitate the definition of our DSL. We use the new DSL to model and synthesize simulation code for a full-fledged MIPS32-based architecture.","PeriodicalId":242721,"journal":{"name":"2018 18th International Conference on Application of Concurrency to System Design (ACSD)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115289129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1