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Digest of Technical Papers., 1990 Symposium on VLSI Circuits最新文献

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A current-mode column comparator circuit for high-speed, low-power on-chip cache-TAG memories 用于高速、低功耗片上缓存- tag存储器的电流模式列比较电路
Digest of Technical Papers., 1990 Symposium on VLSI Circuits Pub Date : 1990-06-07 DOI: 10.1109/VLSIC.1990.111123
M. Suzuki, S. Tachibana, T. Hayashi, A. Watanabe, T. Nishida, S. Shukuri, H. Higuchi, T. Nagano, K. Shimohigashi
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引用次数: 1
An 8 bit 150 MHz CMOS D/A converter with 2 Vp-p wide range output 具有2 Vp-p宽范围输出的8位150 MHz CMOS D/A转换器
Digest of Technical Papers., 1990 Symposium on VLSI Circuits Pub Date : 1990-06-07 DOI: 10.1109/VLSIC.1990.111092
N. Kumazawa, N. Fukushima, N. Ono, N. Sakamoto
{"title":"An 8 bit 150 MHz CMOS D/A converter with 2 Vp-p wide range output","authors":"N. Kumazawa, N. Fukushima, N. Ono, N. Sakamoto","doi":"10.1109/VLSIC.1990.111092","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111092","url":null,"abstract":"An 8-bit digital-to-analog converter with 30-pVs low glitch energy, 2-Vp-p wide-range output from GND, and a 150-MHz sampling rate is described. This device has been achieved on the basis of a new current cell and a biased switch using a 1.4-μm CMOS process. Experimental results for the device are reported","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128242480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 36 ns 1 Mbit CMOS EPROM with new data sensing technique 采用新型数据传感技术的36ns 1mbit CMOS EPROM
Digest of Technical Papers., 1990 Symposium on VLSI Circuits Pub Date : 1990-06-07 DOI: 10.1109/VLSIC.1990.111112
H. Nakai, K. Kanazawa, M. Asano, I. Sato, H. Iwahashi, K. Sakai, M. Yahata, S. Tanaka, N. Tozawa, M. Yatabe, S. Saito
{"title":"A 36 ns 1 Mbit CMOS EPROM with new data sensing technique","authors":"H. Nakai, K. Kanazawa, M. Asano, I. Sato, H. Iwahashi, K. Sakai, M. Yahata, S. Tanaka, N. Tozawa, M. Yatabe, S. Saito","doi":"10.1109/VLSIC.1990.111112","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111112","url":null,"abstract":"A 36-ns, 1-Mb EPROM using a unique pseudodifferential sensing technique for high speed and a new noise immunity technique has been developed. In order to achieve both high speed and small die size, a newly developed pseudodifferential sensing technique with single-ended bit lines (one transistor/cell) and only two reference bit lines has been implemented, instead of a conventional fully differential sensing technique which has the disadvantage of large die size. A new data transfer circuit whose data transfer speed is controlled by an address transition detection pulse is utilized to obtain high noise immunity against power line noise caused by charging or discharging an output capacitance. Using 0.9-μm lithography, a cell size of 3.1 μm×2.9 μm has been achieved, resulting in a small die size of 6.67 mm×6.56 mm. The chip is fabricated by an n-well CMOS double poly-Si process with polycide technology and a single metal","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124568425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 3.5 ns, 2 K×9 self timed SRAM 3.5 ns, 2k×9自定时SRAM
Digest of Technical Papers., 1990 Symposium on VLSI Circuits Pub Date : 1990-06-07 DOI: 10.1109/VLSIC.1990.111089
D. Wendell, J. Demaris, J. Chritz
{"title":"A 3.5 ns, 2 K×9 self timed SRAM","authors":"D. Wendell, J. Demaris, J. Chritz","doi":"10.1109/VLSIC.1990.111089","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111089","url":null,"abstract":"A self-timed SRAM of 18-Kb density has been developed. It has several value-added features for specialty computer CPU applications. This part has an access time of 3.5 ns and a cycle time of less than access. All inputs are registered with respect to the clock positive edge, and read and write operations are internally self-timed. The output latch self-loads internally, thus insuring that data are valid for the entire cycle. The external timing facilities system usage. The part is formed using a self-timed synchronous architecture. An innovative circuit method called postcharge logic that allows a CMOS technology to achieve gate delays roughly equivalent to ECL (emitter coupled logic) gate delays was employed. Gate delays of 105 ps have been observed, compared to 145 ps for a regular CMOS inverter","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122871359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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