M. Suzuki, S. Tachibana, T. Hayashi, A. Watanabe, T. Nishida, S. Shukuri, H. Higuchi, T. Nagano, K. Shimohigashi
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引用次数: 1
Abstract
The authors describe a low-power comparator circuit which is especially useful for on-chip cache-TAG memories. A novel TAG memory comparator circuit scheme, called a current-mode column comparator (CMCC) scheme, is proposed, and the low-power nature of the CMCC without degraded accessing speed is described. An experimental 128-entry by 32-b TAG-memory test chip was fabricated using 0.5-μm BiCMOS technology, and a 3-ns address input to hit delay time was obtained. The power dissipation of the sense amplifiers was reduced by a factor of 10