M. Suzuki, S. Tachibana, T. Hayashi, A. Watanabe, T. Nishida, S. Shukuri, H. Higuchi, T. Nagano, K. Shimohigashi
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引用次数: 1
摘要
作者描述了一种低功耗比较电路，该电路特别适用于片上缓存- tag存储器。提出了一种新的TAG存储比较电路方案，称为电流模式列比较器(CMCC)方案，并描述了CMCC在不降低访问速度的情况下的低功耗特性。采用0.5- μ m BiCMOS技术，制作了一个32-b的128条TAG-memory测试芯片，并获得了一个3-ns的地址输入以获得命中延迟时间。感应放大器的功耗降低了1 / 10
A current-mode column comparator circuit for high-speed, low-power on-chip cache-TAG memories
The authors describe a low-power comparator circuit which is especially useful for on-chip cache-TAG memories. A novel TAG memory comparator circuit scheme, called a current-mode column comparator (CMCC) scheme, is proposed, and the low-power nature of the CMCC without degraded accessing speed is described. An experimental 128-entry by 32-b TAG-memory test chip was fabricated using 0.5-μm BiCMOS technology, and a 3-ns address input to hit delay time was obtained. The power dissipation of the sense amplifiers was reduced by a factor of 10
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