2011 Proceedings of the ESSCIRC (ESSCIRC)最新文献

A 2.56 Gb/s soft RS (255,239) decoder chip for optical communication systems 用于光通信系统的2.56 Gb/s软RS(255,239)解码器芯片

2011 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2011-10-13 DOI: 10.1109/ESSCIRC.2011.6044919

Chih-Hsiang Hsu, Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee

{"title":"A 2.56 Gb/s soft RS (255,239) decoder chip for optical communication systems","authors":"Chih-Hsiang Hsu, Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee","doi":"10.1109/ESSCIRC.2011.6044919","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044919","url":null,"abstract":"Due to the increasing uncertainty of data for higher transmission rate, the Forward Error Correction (FEC) devices need to provide more powerful error correcting capability for optical communication systems. As compared with traditional hard RS decoders, the soft RS decoders can perform substantial coding gain but require much higher hardware complexity. In this paper, a decision-confined algorithm is proposed to enhance the error correcting performance with an area-efficient architecture. The novelty is that, instead of decoding numerous possible transmitted codewords and choosing the most likely one, only one candidate sequence will be decoded after confining the degree of error-locator polynomial Λ(x). For RS (255,239) codes, simulation results confirm that our approach provides 0.4 dB performance gain at 104 CER over the hard RS decoders. The experimental result reveals that our soft decoder can achieve 2.56 Gb/s throughput in standard CMOS 90 nm technology while having similar complexity as a hard decoder. It can fit well for 10–40 Gb/s with 16 RS decoders in optical fiber systems and 2.5 Gb/s GPON applications.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115271642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

A fast self-reacting capacitor-less low-dropout regulator 一种快速自反应无电容低差调节器

2011 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2011-10-13 DOI: 10.1109/ESSCIRC.2011.6044985

Chia-Min Chen, C. Hung

引用次数: 27

A 1.95GHz sub-1dB NF, +40dBm OIP3 WCDMA LNA with variable attenuation in SiGe:C BiCMOS 一种1.95GHz sub-1dB NF， +40dBm OIP3, SiGe:C BiCMOS可变衰减的WCDMA LNA

2011 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2011-10-13 DOI: 10.1109/ESSCIRC.2011.6044948

J. Bergervoet, D. Leenaerts, G. D. Jong, E. V. D. Heijden, J. Lobeek, A. Simin

引用次数: 5

A standard cell based all-digital Time-to-Digital Converter with reconfigurable resolution and on-line background calibration 一个基于标准单元的全数字时间-数字转换器，具有可重构的分辨率和在线背景校准

2011 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2011-10-13 DOI: 10.1109/ESSCIRC.2011.6044960

Kameswaran Vengattaramane, J. Borremans, M. Steyaert, J. Craninckx

引用次数: 8

A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence 具有自生成随机序列的2.97 Gb/s抗dpa AES引擎

2011 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2011-10-13 DOI: 10.1109/ESSCIRC.2011.6044917

Po-Chun Liu, Ju-Hung Hsiao, Hsie-Chia Chang, Chen-Yi Lee

引用次数: 13

A tunable transconductor for analog amplification and filtering based on double-gate organic TFTs 一种基于双栅有机tft的可调谐模拟放大和滤波变换器

2011 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2011-10-13 DOI: 10.1109/ESSCIRC.2011.6044995

D. Raiteri, F. Torricelli, E. Cantatore, A. Roermund

引用次数: 23

An energy-efficient 15-bit capacitive sensor interface 高效的15位电容式传感器接口

2011 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2011-10-13 DOI: 10.1109/ESSCIRC.2011.6044962

Z. Tan, M. Pertijs, G. Meijer

引用次数: 7

DC-DC converter assisted two-stage amplifier in organic thin-film transistor technology on foil 箔上有机薄膜晶体管技术中的DC-DC变换器辅助两级放大器

2011 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2011-10-13 DOI: 10.1109/ESSCIRC.2011.6044994

H. Marien, M. Steyaert, E. Veenendaal, P. Heremans

引用次数: 17

Merged two-stage power converter with soft charging switched-capacitor stage in 180 nm CMOS 180nm CMOS软充电开关电容级合并两级功率变换器

2011 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2011-10-13 DOI: 10.1109/ESSCIRC.2011.6045011

R. Pilawa-Podgurski, D. Perreault

引用次数: 140

A 0.06-psRMS SSC-induced jitter, ΔΣ-dithering-free, 6-GHz spread-spectrum clock generator for serial-ATA generation 用于串行ata生成的0.06 psrms ssc诱导抖动，ΔΣ-dithering-free, 6 ghz扩频时钟发生器

2011 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2011-10-13 DOI: 10.1109/ESSCIRC.2011.6045003

Cheng-Liang Hung, Kuo-Hsing Cheng, Yu-Chen Lin, Bo-Qian Jiang, C. Fan, Chi-Yang Chang

{"title":"A 0.06-psRMS SSC-induced jitter, ΔΣ-dithering-free, 6-GHz spread-spectrum clock generator for serial-ATA generation","authors":"Cheng-Liang Hung, Kuo-Hsing Cheng, Yu-Chen Lin, Bo-Qian Jiang, C. Fan, Chi-Yang Chang","doi":"10.1109/ESSCIRC.2011.6045003","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6045003","url":null,"abstract":"A 90-nm CMOS, 6-GHz spread-spectrum clock generator (SSCG) showing low jitter and the feasible electromagnetic interference (EMI) reduction is presented. Forsaking the commonly used ΔΣ technique for the average fractional-N ratios by the dithering, the proposed SSCG uses a phase-rotating technique to realize truly fractional division ratios, and creates the spread-spread clocking (SSC) by modulating the fractional-N ratios. The phase-rotating technique effectively calibrates instantaneous timing error and shows ignorable quantization error. Operating at a 6-GHz clock rate, the measured RMS jitter with and without a 0.5% (5000-ppm) down-spreading spectrum are 0.77 ps and 0.71 ps, respectively, showing a significant improvement in the suppressed sub-1ps RMS jitter and the mere increase in RMS jitter of 0.06 ps while implementing SSC. As the serial AT attachment (SATA) standard suggesting the 100 kHz-RBW for the instruments, the measured power attenuation of EMI is 16.12 dB under a 5000-ppm frequency deviation. The chip core area is less than 0.55 × 0.45 mm2, and the core power consumption is 27.7 mW at a 1.0-V supply.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130352638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0