2022 International Conference on Field-Programmable Technology (ICFPT)最新文献

Energy Efficient Design of Coarse-Grained Reconfigurable Architectures: Insights, Trends and Challenges 粗粒度可重构架构的节能设计:见解、趋势和挑战

2022 International Conference on Field-Programmable Technology (ICFPT) Pub Date : 2022-12-05 DOI: 10.1109/ICFPT56656.2022.9974339

Ensieh Aliagha, D. Göhringer

引用次数: 1

Boosting Domain-Specific Debug Through Inter-frame Compression 通过帧间压缩增强特定于域的调试

2022 International Conference on Field-Programmable Technology (ICFPT) Pub Date : 2022-12-05 DOI: 10.1109/ICFPT56656.2022.9974385

Zakary Nafziger, Martin Chua, D. H. Noronha, S. Wilton

{"title":"Boosting Domain-Specific Debug Through Inter-frame Compression","authors":"Zakary Nafziger, Martin Chua, D. H. Noronha, S. Wilton","doi":"10.1109/ICFPT56656.2022.9974385","DOIUrl":"https://doi.org/10.1109/ICFPT56656.2022.9974385","url":null,"abstract":"Acceleration of machine learning models is proving to be an important application for FPGAs. Unfortunately, debugging such models during training or inference is difficult. Software simulations of a machine learning system may be of insufficient detail to provide meaningful debug insight, or may require infeasibly long run-times. Thus, it is often desirable to debug the accelerated model while it is running on real hardware. Effective on-chip debug often requires instrumenting a design with additional circuitry to store run-time data, consuming valuable chip resources. Previous work has developed methods to perform lossy compression of signals by exploiting machine learning specific knowledge, thereby increasing the amount of debug context that can be stored in an on-chip trace buffer. However, all prior work compresses each successive element in a signal of interest independently. Since debug signals may have temporal similarity in many machine learning applications there is an opportunity to further increase trace buffer utilization. In this paper, we present an architecture to perform lossless temporal compression in addition to the existing lossy element-wise compression. We show that, when applied to a typical machine learning algorithm in realistic debug scenarios, we are able to store twice as much information in an on-chip buffer while increasing the total area of the debug instrument by approximately 25%. The impact is that, for a given instrumentation budget, a significantly larger trace window is available during debug, possibly allowing a designer to narrow down the root cause of a bug faster.","PeriodicalId":239314,"journal":{"name":"2022 International Conference on Field-Programmable Technology (ICFPT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123397351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Exploring Inter-tile Connectivity for HPC-oriented CGRA with Lower Resource Usage 探索面向高性能计算的低资源占用CGRA的层间连接

2022 International Conference on Field-Programmable Technology (ICFPT) Pub Date : 2022-12-05 DOI: 10.1109/ICFPT56656.2022.9974525

B. Adhi, Carlos Cortes, Tomohiro Ueno, Y. Tan, Takuya Kojima, Artur Podobas, K. Sano

引用次数: 2

The Impact of Hardware Folding on Dependability in Spaceborne FPGA-based Neural Networks 硬件折叠对星载fpga神经网络可靠性的影响

2022 International Conference on Field-Programmable Technology (ICFPT) Pub Date : 2022-12-05 DOI: 10.1109/ICFPT56656.2022.9974551

I. Souvatzoglou, D. Agiakatsikas, G. Antonopoulos, V. Vlagkoulis, Aitzan Sari, Athanasios Papadimitriou, M. Psarakis

{"title":"The Impact of Hardware Folding on Dependability in Spaceborne FPGA-based Neural Networks","authors":"I. Souvatzoglou, D. Agiakatsikas, G. Antonopoulos, V. Vlagkoulis, Aitzan Sari, Athanasios Papadimitriou, M. Psarakis","doi":"10.1109/ICFPT56656.2022.9974551","DOIUrl":"https://doi.org/10.1109/ICFPT56656.2022.9974551","url":null,"abstract":"Commercial SRAM-based field-programmable gate arrays (FPGAs) are becoming popular computing platforms for building efficient Neural Network (NN) accelerators for space missions. FPGAs can implement custom NN architectures that are tailored to the requirements of the mission to improve the performance-to-watt ratio of the design. However, SRAM FPGAs are vulnerable to radiation-induced Single Event Upsets (SEUs), imposing significant design-for-reliability challenges. In this work, we study the impact of hardware folding on the dependability of Binarised NN (BNN) FPGA accelerators. Hard-ware folding configures the level of resource sharing in the design. We implemented three design versions of a BNN that performs image classification. The BNNs were generated with FINN, an open-source framework for developing quantised NNs on AMD-Xilinx FPGAs. The BNNs were implemented on a Zynq-7020 system-on-chip FPGA and tested with configuration memory fault injection experiments to estimate their SEU vulnerability. The three BNN design versions have a maximum (Max), medium (Med), and minimum (Min) folding factor, respectively. Assuming a Low Earth Orbit (LEO), our results show that the Med BNN has the highest Mean Time Between Failure (MTBF) and the Min has the lowest MTBF. However, Min has the highest Mean Executions Between Failure (MEBF) due to its high computational performance.","PeriodicalId":239314,"journal":{"name":"2022 International Conference on Field-Programmable Technology (ICFPT)","volume":"2020 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114536688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fast and Flexible FPGA Development using Hierarchical Partial Reconfiguration 基于分层部分重构的快速灵活FPGA开发

2022 International Conference on Field-Programmable Technology (ICFPT) Pub Date : 2022-12-05 DOI: 10.1109/ICFPT56656.2022.9974201

Dongjoon Park, Yuanlong Xiao, A. DeHon

{"title":"Fast and Flexible FPGA Development using Hierarchical Partial Reconfiguration","authors":"Dongjoon Park, Yuanlong Xiao, A. DeHon","doi":"10.1109/ICFPT56656.2022.9974201","DOIUrl":"https://doi.org/10.1109/ICFPT56656.2022.9974201","url":null,"abstract":"To address slow FPGA compilation, researchers have proposed to run separate compilations for smaller design components in parallel. This approach provides small pages on the FPGA, allowing users to separately generate partial designs on the pages and load them together. However, this method either forces users to manually decompose a design into small components that fit in small, fixed-sized pages or to use large, fixed-sized pages, reducing the potential compilation speedup benefits. This restriction often results in suboptimal decomposition of a design or diminishes productivity. To overcome these limitations, we utilize the recently supported Hierarchical Partial Reconfiguration technology from Xilinx to generate a more flexible framework. Depending on the size of user designs, our framework provides larger pages that are hierarchically recombined from multiple smaller pages. This flexibility relieves users of the burden to decompose the original design and offers more opportunities for design-space exploration. When tested on the ZCU102 embedded platform with the Rosetta HLS benchmarks, our system achieves $1.4-4.9times$ mapped application performance improvement compared to the system with fixed-sized pages while still compiling in 2–5 minutes $(2.2-5.3times$ faster than the vendor tool).","PeriodicalId":239314,"journal":{"name":"2022 International Conference on Field-Programmable Technology (ICFPT)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124546151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Hardware-Efficient FPGA-Based Approximate Multipliers for Error-Tolerant Computing 基于fpga的容错计算的硬件高效近似乘法器

2022 International Conference on Field-Programmable Technology (ICFPT) Pub Date : 2022-12-05 DOI: 10.1109/ICFPT56656.2022.9974399

Shangshang Yao, L. Zhang

{"title":"Hardware-Efficient FPGA-Based Approximate Multipliers for Error-Tolerant Computing","authors":"Shangshang Yao, L. Zhang","doi":"10.1109/ICFPT56656.2022.9974399","DOIUrl":"https://doi.org/10.1109/ICFPT56656.2022.9974399","url":null,"abstract":"With the increasing demand for data processing, approximate computing is widely used in various fault-tolerant applications such as image processing, computer vision and machine learning. These applications also require a huge number of multiplication operations. In this paper, we are mainly oriented to the softcore approximate multiplier which is implemented on FPGA via encoding the INIT parameter values in the Look-Up-Table (LUT) primitives. Three approximate multipliers with associated carry chain are presented in the manner of reducing LUTs from proposed exact multiplier. An approximate multiplier without carry chain is also presented to further reduce the multiplier's critical path delay and power consumption. We also present an accuracy configurable adder to build high-order approximate multipliers for architectural space exploration. The resolution of the state-of-the-art Mean Relative Error Distance (MRED) and Power-Delay Product (PDP) pareto front is improved and the approximate multiplier we proposed achieves 24.4%, 52.9% and 56.4% reduction in latency, area, and power over the soft multiplier IP core, respectively. Finally, we apply the proposed approximate multiplier design to image processing and convolutional neural networks (CNNs). Compared to advanced approximate multipliers, it offers less energy consumption and area while remaining acceptable qualities. Our designs are open sourced at https://github.com/Yaoshangshang96/FPGA-based_approx_mult to assist further reproducing and development.","PeriodicalId":239314,"journal":{"name":"2022 International Conference on Field-Programmable Technology (ICFPT)","volume":"60 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114021718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Dual-Triangular QR Decomposition with Global Acceleration and Partially Q-Rotation Skipping 具有全局加速和部分q旋转跳变的双三角形QR分解

2022 International Conference on Field-Programmable Technology (ICFPT) Pub Date : 2022-12-05 DOI: 10.1109/ICFPT56656.2022.9974402

Rui Fang, Siyang Jiang, Hsi-Wen Chen, Wei Ding, Ming-Syan Chen

引用次数: 0

A Lightweight FPGA-based IDS-ECU Architecture for Automotive CAN 一种基于fpga的汽车CAN轻量化IDS-ECU架构

2022 International Conference on Field-Programmable Technology (ICFPT) Pub Date : 2022-12-05 DOI: 10.1109/ICFPT56656.2022.9974508

Shashwat Khandelwal, Shanker Shreejith

{"title":"A Lightweight FPGA-based IDS-ECU Architecture for Automotive CAN","authors":"Shashwat Khandelwal, Shanker Shreejith","doi":"10.1109/ICFPT56656.2022.9974508","DOIUrl":"https://doi.org/10.1109/ICFPT56656.2022.9974508","url":null,"abstract":"Recent years have seen an exponential rise in complex software-driven functionality in vehicles, leading to a rising number of electronic control units (ECUs), network capabilities, and interfaces. These expanded capabilities also bring-in new planes of vulnerabilities making intrusion detection and management a critical capability; however, this can often result in more ECUs and network elements due to the high computational overheads. In this paper, we present a consolidated ECU architecture incorporating an Intrusion Detection System (IDS) for Automotive Controller Area Network (CAN) along with traditional ECU functionality on an off-the-shelf hybrid FPGA device, with near-zero overhead for the ECU functionality. We propose two quantised multi-layer perceptrons (QMLP's) as isolated IDSs for detecting a range of attack vectors including Denial-of-Service, Fuzzing and Spoofing, which are accelerated using off-the-shelf deep-learning processing unit (DPU) IP block from Xilinx, operating fully transparently to the software on the ECU. The proposed models achieve the state-of-the-art classification accuracy for all the attacks, while we observed a 15x reduction in power consumption when compared against the GPU-based implementation of the same models quantised using Nvidia libraries. We also achieved a 2.3x speed up in per-message processing latency (at 0.24 ms from the arrival of a CAN message) to meet the strict end-to-end latency on critical CAN nodes and a 2.6x reduction in power consumption for inference when compared to the state-of-the-art IDS models on embedded IDS and loosely coupled IDS accelerators (GPUs) discussed in the literature.","PeriodicalId":239314,"journal":{"name":"2022 International Conference on Field-Programmable Technology (ICFPT)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131407079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

ZHW: A Numerical CODEC for Big Data Scientific Computation 面向大数据科学计算的数字编解码器

2022 International Conference on Field-Programmable Technology (ICFPT) Pub Date : 2022-12-05 DOI: 10.1109/ICFPT56656.2022.9974258

Michael Barrow, Zhuanhao Wu, Scott Lloyd, M. Gokhale, Hiren D. Patel, P. Lindstrom

引用次数: 1

Autonomous driving system with feature extraction using a binarized autoencoder 基于二值化自编码器的自动驾驶系统特征提取

2022 International Conference on Field-Programmable Technology (ICFPT) Pub Date : 2022-12-05 DOI: 10.1109/ICFPT56656.2022.9974267

Kota Hisafuru, Ryotaro Negishi, Soma Kawakami, D. Sato, Kazuki Yamashita, Keisuke Fukada, N. Togawa

引用次数: 0