2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)最新文献_第3页

A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench 多试验台模拟设计中一种新颖高效的贝叶斯优化方法

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/ASP-DAC52403.2022.9712590

Jingyao Zhao, Changhao Yan, Zhaori Bi, Fan Yang, Xuan Zeng, Dian Zhou

引用次数: 2

Linear Feedback Shift Register Reseeding for Stochastic Circuit Repairing and Minimization 随机电路修复与最小化的线性反馈移位寄存器补播

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/ASP-DAC52403.2022.9712512

Chen Wang, Weikang Qian

引用次数: 0

CGRA Mapping Using Zero-Suppressed Binary Decision Diagrams 使用零抑制二值决策图的CGRA映射

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/asp-dac52403.2022.9712571

Rami Beidas, J. Anderson

引用次数: 3

Automating Analog Constraint Extraction: From Heuristics to Learning: (Invited Paper) 自动化模拟约束提取:从启发式到学习:(特邀论文)

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/ASP-DAC52403.2022.9712488

Keren Zhu, Hao Chen, Mingjie Liu, D. Pan

引用次数: 4

Automated Detection of Spatial Memory Safety Violations for Constrained Devices 约束设备空间存储安全违规的自动检测

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/asp-dac52403.2022.9712570

Sören Tempel, V. Herdt, R. Drechsler

引用次数: 4

Dynamic CNN Accelerator Supporting Efficient Filter Generator with Kernel Enhancement and Online Channel Pruning 动态CNN加速器支持有效的滤波器生成器与核增强和在线通道修剪

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/ASP-DAC52403.2022.9712483

Chen Tang, Wenyu Sun, Wenxun Wang, Yongpan Liu

引用次数: 2

Exploring ILP for VLIW Architecture by Quantified Modeling and Dynamic Programming-Based Instruction Scheduling 通过量化建模和基于动态规划的指令调度探索VLIW体系结构的ILP

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/ASP-DAC52403.2022.9712500

Can Deng, Zhaoyun Chen, Yang Shi, Xichang Kong, Mei Wen

引用次数: 1

Optimal Loop Tiling for Minimizing Write Operations on NVMs with Complete Memory Latency Hiding 在完全内存延迟隐藏的情况下，最小化nvm写操作的最佳循环平铺

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/ASP-DAC52403.2022.9712532

Rui Xu, E. Sha, Qingfeng Zhuge, Yuhong Song, Jingzhi Lin

{"title":"Optimal Loop Tiling for Minimizing Write Operations on NVMs with Complete Memory Latency Hiding","authors":"Rui Xu, E. Sha, Qingfeng Zhuge, Yuhong Song, Jingzhi Lin","doi":"10.1109/ASP-DAC52403.2022.9712532","DOIUrl":"https://doi.org/10.1109/ASP-DAC52403.2022.9712532","url":null,"abstract":"Non-volatile memory (NVM) is expected to be the second level memory (named remote memory) in two-level memory hierarchy in the future. However, NVM has the limited write endurance, thus it is vital to reduce the number of write operations on NVM. Meanwhile, in two-level memory hierarchy, prefetch is widely used for fetching certain data before it is actually required, to hide the remote memory access latency. In general, large-scale nested loop is the performance bottleneck in one program due to the write operations on NVM caused by the first level memory (named local memory) miss and data reuse. Loop tiling is the key technique for grouping iterations so as to reduce the communication with remote memory used in compiler. In this paper, we propose a new loop tiling approach for minimizing the write operations on NVMs and completely hiding the NVM access latency. Specifically, we introduce a series of theorems to help loop tiling. Then, a legal tile shape and an optimal tile size selection strategy is proposed according to data dependency and local memory capacity. Furthermore, we propose a pipeline scheduling policy to completely hide the remote memory latency. Extensive experiments show that the proposed techniques can reduce write operations on NVMs by 95.1% on average, and NVM latency can be completely hidden.","PeriodicalId":239260,"journal":{"name":"2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115433677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

FORTIFY: Analytical Pre-Silicon Side-Channel Characterization of Digital Designs 强化:数字设计的分析前硅侧通道特性

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/ASP-DAC52403.2022.9712551

A. V. Lakshmy, C. Rebeiro, S. Bhunia

引用次数: 1

HEALM: Hardware-Efficient Approximate Logarithmic Multiplier with Reduced Error 具有最小误差的硬件效率近似对数乘法器

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/ASP-DAC52403.2022.9712543

Shuyuan Yu, Maliha Tasnim, S. Tan

{"title":"HEALM: Hardware-Efficient Approximate Logarithmic Multiplier with Reduced Error","authors":"Shuyuan Yu, Maliha Tasnim, S. Tan","doi":"10.1109/ASP-DAC52403.2022.9712543","DOIUrl":"https://doi.org/10.1109/ASP-DAC52403.2022.9712543","url":null,"abstract":"In this work, we propose a new approximate logarithm multipliers (ALM) based on a novel error compensation scheme. The proposed hardware-efficient ALM, named HEALM, first determines the truncation width for mantissa summation in ALM. Then the error compensation or reduction is performed via a lookup table, which stores reduction factors for different regions of input operands. This is in contrast to an existing approach, in which error reduction is performed independently of the width truncation of mantissa summation. As a result, the new design will lead to more accurate result with both reduced area and power. Furthermore, different from existing approaches which will either introduce resource overheads when doing error improvement or lose accuracy when saving area and power, HEALM can improve accuracy and resource consumption at the same time. Our study shows that 8-bit HEALM can achieve up to 2.92%, 9.30%, 16.08%, 17.61% improvement in mean error, peak error, area, power consumption respectively over REALM, which is the state of art work with the same number of bits truncated. We also propose a single error coefficient mode named HEALM-TA-S, which improves the ALM design with a truncation adder (TA) for mantissa summation. Furthermore, we evaluate the proposed HEALM design in a discrete cosine transformation (DCT) application. The result shows that with different values of k, HEALM-TA can improve the image quality upon the ALM baseline by 7.8~17.2dB in average and HEALM-SOA can improve 2.9~15.8dB in average, respectively. Besides, HEALM-TA and HEALM-SOA outperform all the state of art works with k = 2, 3, 4 on the image quality. And the single coefficient mode, HEALM-TA-S, can improve the image quality upon the baseline up to 4.1dB in average with extremely low resource consumption.","PeriodicalId":239260,"journal":{"name":"2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124003005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1