CGRA Mapping Using Zero-Suppressed Binary Decision Diagrams

Abstract

The restricted routing networks of coarse-grained reconfigurable arrays (CGRAs) have motivated CAD developers to utilize exact solutions, such as integer linear programming (ILP), in formu-lating and solving the mapping problem. Such so-lutions that rely on general purpose optimizers have not been shown to scale. In this work, we formu-late CGRA mapping as a solution enumeration and selection problem, relying on the efficiency of zero-suppressed binary decision diagrams (ZDDs) [22] to capture the solution space. For small-to-moderate size problems, it is possible to capture every possible map-ping in a few megabytes. For larger problems, thou-sands if not millions of solutions can be enumerated. The final mapping is a simple linear-time DAG traver-sal of the enumeration ZDD. The proposed solution was implemented in the CGRA-ME [6] framework. A speedup of two orders of magnitude was obtained when compared with past solutions targeting smaller CGRA devices. Larger devices beyond the capacity of those solutions are now accessible.