IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012)最新文献_第3页

VARIUS-NTV: A microarchitectural model to capture the increased sensitivity of manycores to process variations at near-threshold voltages VARIUS-NTV:一种微架构模型，用于捕获多核在接近阈值电压时对工艺变化增加的灵敏度

IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012) Pub Date : 2012-06-25 DOI: 10.1109/DSN.2012.6263951

Ulya R. Karpuzcu, K. Kolluru, N. Kim, J. Torrellas

{"title":"VARIUS-NTV: A microarchitectural model to capture the increased sensitivity of manycores to process variations at near-threshold voltages","authors":"Ulya R. Karpuzcu, K. Kolluru, N. Kim, J. Torrellas","doi":"10.1109/DSN.2012.6263951","DOIUrl":"https://doi.org/10.1109/DSN.2012.6263951","url":null,"abstract":"Near-Threshold Computing (NTC), where the supply voltage is only slightly higher than the threshold voltage of transistors, is a promising approach to attain energy-efficient computing. Unfortunately, compared to the conventional Super-Threshold Computing (STC), NTC is more sensitive to process variations, which results in higher power consumption and lower frequencies than would otherwise be possible, and potentially a non-negligible fault rate. To help address variations at NTC at the architecture level, this paper presents the first microarchitectural model of process variations for NTC. The model, called VARIUS-NTV, extends the existing VARIUS variation model. Its key aspects include: (i) adopting a gate-delay model and an SRAM cell type that are tailored to NTC, (ii) modeling SRAM failure modes emerging at NTC, and (iii) accounting for the impact of leakage in SRAM models. We evaluate a simulated 11nm, 288-core tiled manycore at both NTC and STC. The results show higher frequency and power variations within the NTC chip. For example, the maximum difference in on-chip tile frequency is ≈2.3× at STC and ≈3.7× at NTC. We also validate our model against an experimental chip.","PeriodicalId":236791,"journal":{"name":"IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132839519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 94

Finite horizon analysis of infinite CTMDPs 无限CTMDPs的有限视界分析

IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012) Pub Date : 2012-06-25 DOI: 10.1109/DSN.2012.6263929

P. Buchholz

引用次数: 3

A cost-based heterogeneous recovery scheme for distributed storage systems with RAID-6 codes 一种基于成本的分布式存储系统RAID-6码异构恢复方案

IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012) Pub Date : 2012-06-25 DOI: 10.1109/DSN.2012.6263934

Yunfeng Zhu, P. Lee, Liping Xiang, Yinlong Xu, L. Gao

{"title":"A cost-based heterogeneous recovery scheme for distributed storage systems with RAID-6 codes","authors":"Yunfeng Zhu, P. Lee, Liping Xiang, Yinlong Xu, L. Gao","doi":"10.1109/DSN.2012.6263934","DOIUrl":"https://doi.org/10.1109/DSN.2012.6263934","url":null,"abstract":"Modern distributed storage systems provide large-scale, fault-tolerant data storage. To reduce the probability of data unavailability, it is important to recover the lost data of any failed storage node efficiently. In practice, storage nodes are of heterogeneous types and have different transmission bandwidths. Thus, traditional recovery solutions that simply minimize the number of data blocks being read may no longer be optimal in a heterogeneous environment. We propose a cost-based heterogeneous recovery (CHR) algorithm for RAID-6-coded storage systems. We formulate the recovery problem as an optimization model in which storage nodes are associated with generic costs. We narrow down the solution space of the model to make it practically tractable, while still achieving the global optimal solution in most cases. We implement different recovery algorithms and conduct testbed experiments on a real networked storage system with heterogeneous storage devices. We show that our CHR algorithm reduces the total recovery time of existing recovery solutions in various scenarios.","PeriodicalId":236791,"journal":{"name":"IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130381317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 27

Filtering log data: Finding the needles in the Haystack 过滤日志数据:大海捞针

IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012) Pub Date : 2012-06-25 DOI: 10.1109/DSN.2012.6263948

Li Yu, Ziming Zheng, Z. Lan, T. Jones, J. Brandt, A. Gentile

引用次数: 17

RePRAM: Re-cycling PRAM faulty blocks for extended lifetime RePRAM:回收PRAM故障块以延长使用寿命

IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012) Pub Date : 2012-06-25 DOI: 10.1109/DSN.2012.6263950

Jie Chen, Guru Venkataramani, H. H. Huang

{"title":"RePRAM: Re-cycling PRAM faulty blocks for extended lifetime","authors":"Jie Chen, Guru Venkataramani, H. H. Huang","doi":"10.1109/DSN.2012.6263950","DOIUrl":"https://doi.org/10.1109/DSN.2012.6263950","url":null,"abstract":"As main memory systems begin to face the scaling challenges from DRAM technology, future computer systems need to adapt to the emerging memory technologies like Phase-Change Memory (PCM or PRAM). While these newer technologies offer advantages such as storage density, non-volatility, and low energy consumption, they are constrained by limited write endurance that becomes more pronounced with process variation. In this paper, we propose a novel PRAM-based main memory system, RePRAM (Recycling PRAM), which leverages a group of faulty pages and recycles them in a managed way to significantly extend the PRAM lifetime while minimizing the performance impact. In particular, we explore two different dimensions of dynamic redundancy levels and group sizes, and design low-cost hardware and software support for RePRAM. Our proposed scheme involves minimal hardware modifications (that have less than 1% on-chip and off-chip area overheads). Also, our schemes can improve the PRAM lifetime by up to 43× (times) over a chip with no error correction capabilities, and outperform prior schemes such as DRM and ECP at a small fraction of the hardware cost. The performance overhead resulting from our scheme is less than 7% on average across 21 applications from SPEC2006, Splash-2, and PARSEC benchmark suites.","PeriodicalId":236791,"journal":{"name":"IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121949134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

Mitigating random variation with spare RIBs: Redundant intermediate bitslices 用备用肋减轻随机变化:冗余的中间位片

IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012) Pub Date : 2012-06-25 DOI: 10.1109/DSN.2012.6263952

David J. Palframan, N. Kim, Mikko H. Lipasti

引用次数: 5

RDIS: A recursively defined invertible set scheme to tolerate multiple stuck-at faults in resistive memory RDIS:一种递归定义的可逆集合方案，用于在电阻内存中容忍多个卡滞故障

IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012) Pub Date : 2012-06-25 DOI: 10.1109/DSN.2012.6263949

R. Melhem, R. Maddah, Sangyeun Cho

{"title":"RDIS: A recursively defined invertible set scheme to tolerate multiple stuck-at faults in resistive memory","authors":"R. Melhem, R. Maddah, Sangyeun Cho","doi":"10.1109/DSN.2012.6263949","DOIUrl":"https://doi.org/10.1109/DSN.2012.6263949","url":null,"abstract":"With their potential for high scalability and density, resistive memories are foreseen as a promising technology that overcomes the physical limitations confronted by charge-based DRAM and flash memory. Yet, a main burden towards the successful adoption and commercialization of resistive memories is their low cell reliability caused by process variation and limited write endurance. Typically, faulty and worn-out cells are permanently stuck at either `0' or `1'. To overcome the challenge, a robust error correction scheme that can recover from many hard faults is required. In this paper, we propose and evaluate RDIS, a novel scheme to efficiently tolerate memory stuck-at faults. RDIS allows for the correct retrieval of data by recursively determining and efficiently keeping track of the positions of the bits that are stuck at a value different from the ones that are written, and then, at read time, by inverting the values read from those positions. RDIS is characterized by a very low probability of failure that increases slowly with the relative increase in the number of faults. Moreover, RDIS tolerates many more faults than the best existing scheme-by up to 95% on average at the same overhead level.","PeriodicalId":236791,"journal":{"name":"IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125745800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 42

A cross-layer approach for IP network protection IP网络保护的跨层方法

IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012) Pub Date : 2012-06-25 DOI: 10.1109/DSN.2012.6263944

Qiang Zheng, J. Zhao, G. Cao

引用次数: 4

Scalable deferred update replication 可伸缩延迟更新复制

IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012) Pub Date : 2012-06-25 DOI: 10.1109/DSN.2012.6263931

Daniele Sciascia, F. Pedone, F. Junqueira

引用次数: 66

Safeguarding academic accounts and resources with the University Credential Abuse Auditing System 利用大学证书滥用审计制度保护学术帐户和资源

IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012) Pub Date : 2012-06-25 DOI: 10.1109/DSN.2012.6263961

Jing Zhang, R. Berthier, Will Rhee, Michael Bailey, P. Pal, F. Jahanian, W. Sanders

引用次数: 17