2018 IEEE 13th International Symposium on Industrial Embedded Systems (SIES)最新文献_第2页

Fault- Tolerance Support for Mobile Robotic Applications 移动机器人应用的容错支持

2018 IEEE 13th International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2018-06-01 DOI: 10.1109/SIES.2018.8442098

Manos Koutsoubelias, S. Lalis

{"title":"Fault- Tolerance Support for Mobile Robotic Applications","authors":"Manos Koutsoubelias, S. Lalis","doi":"10.1109/SIES.2018.8442098","DOIUrl":"https://doi.org/10.1109/SIES.2018.8442098","url":null,"abstract":"The advent of powerful yet also affordable mobile robotic platforms will spur a new generation of computer-driven applications that employ multiple mobile robots to perform a large variety of missions. This prospect has lead to the emergence of corresponding programming models that aim to ease the development of such applications, allowing a more straightforward exploitation of the resources that are available on these platforms. But fault-tolerance remains a challenging issue due to the inherent dynamics of such cyber-physical systems. Notably, some of the actions that are performed in the context of such executions cannot be easily undone, while in other cases it may be problematic to automatically redo certain actions without the explicit control of the application. The desired functionality cannot be achieved by applying traditional fault-tolerance schemes out-of-the-box; these need to be combined and extended in a suitable manner. In this paper, we present system-level support designed to provide transparent fault-tolerance for applications that coordinate multiple mobile robots in a centralized way. We discuss a concrete implementation of the proposed approach as part of an existing programming framework. Also, we present an evaluation of the respective overhead for individual runtime operations as well as for indicative application scenarios with and without failures.","PeriodicalId":236091,"journal":{"name":"2018 IEEE 13th International Symposium on Industrial Embedded Systems (SIES)","volume":"55 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130366983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

EventQueue: An Event based and Priority aware Interprocess Communication for Embedded Systems 嵌入式系统中基于事件和优先级感知的进程间通信

2018 IEEE 13th International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2018-06-01 DOI: 10.1109/SIES.2018.8442089

Fabian Mauroner, M. Baunach

引用次数: 0

Preliminary Evaluation of High-level Synthesis Tools - Xilinx Vivado and PandA Bambu 高级合成工具——Xilinx Vivado和PandA Bambu的初步评价

2018 IEEE 13th International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2018-06-01 DOI: 10.1109/SIES.2018.8442100

Christian Fibich, Stefan Tauner, Peter Rössler, M. Horauer, Herbert Taucher, Martin Matschnig

引用次数: 5

On the Consensus Mechanisms of Blockchain/DLT for Internet of Things 论面向物联网的区块链/DLT共识机制

2018 IEEE 13th International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2018-06-01 DOI: 10.1109/SIES.2018.8442076

Qingqiang He, Nan Guan, Mingsong Lv, W. Yi

引用次数: 27

Parameter-Aware Energy Models for Embedded-System Peripherals 嵌入式系统外设的参数感知能量模型

2018 IEEE 13th International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2018-06-01 DOI: 10.1109/SIES.2018.8442096

Daniel Friesel, Markus Buschhoff, O. Spinczyk

引用次数: 7

Network Calculus-based Timing Analysis of AFDX networks with Strict Priority and TSN/BLS Shapers 基于网络计算的具有严格优先级和TSN/BLS形状的AFDX网络时序分析

2018 IEEE 13th International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2018-06-01 DOI: 10.1109/SIES.2018.8442080

A. Finzi, A. Mifdaoui, F. Frances, E. Lochin

{"title":"Network Calculus-based Timing Analysis of AFDX networks with Strict Priority and TSN/BLS Shapers","authors":"A. Finzi, A. Mifdaoui, F. Frances, E. Lochin","doi":"10.1109/SIES.2018.8442080","DOIUrl":"https://doi.org/10.1109/SIES.2018.8442080","url":null,"abstract":"A homogeneous avionic communication architecture based on the AFDX supporting mixed-criticality applications will bring significant advantages, i.e., easier maintenance and reduced costs. To cope with this emerging issue, the AFDX may integrate multiple traffic classes: Safety-Critical Traffic (SCT) with hard real-time constraints, Rate-Constrained (RC) traffic requiring bounded latencies and Best Effort (BE) traffic with no delivery constraints. These traffic classes are managed based on a Non-Preemptive Strict Priority (NP-SP) Scheduler, where the highest priority traffic (SCT) is shaped with a Burst Limiting Shaper (BLS). The latter has been defined by the Time Sensitive Networking (TSN) task group to limit the impact of high priority flows on lower priority ones. This paper proposes a Network Calculus-based approach to compute the end-to-end delay bounds of SCT and RC classes. We consider the impact of the BLS and the multi-hop network architecture. We also provide proofs of service curves guaranteed to SCT and RC classes, needed to derive delay bounds with Network Calculus. The proposed approach is evaluated on a realistic AFDX configuration. Results show the efficiency of incorporating the TSN/BLS on top of a NP-SP scheduler in the AFDX to noticeably enhance the RC delay bounds while guaranteeing the SCT deadline, in comparison to an AFDX implementing only a NP-SP scheduler.","PeriodicalId":236091,"journal":{"name":"2018 IEEE 13th International Symposium on Industrial Embedded Systems (SIES)","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116599703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Simulation Model and Environment for Mixed-Criticality Networked Multi-Core Chips 混合临界网络化多核芯片仿真模型与环境

2018 IEEE 13th International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2018-06-01 DOI: 10.1109/SIES.2018.8442102

M. Abuteir, Zaher Owda, Hamidreza Ahmadian, R. Obermaisser

{"title":"Simulation Model and Environment for Mixed-Criticality Networked Multi-Core Chips","authors":"M. Abuteir, Zaher Owda, Hamidreza Ahmadian, R. Obermaisser","doi":"10.1109/SIES.2018.8442102","DOIUrl":"https://doi.org/10.1109/SIES.2018.8442102","url":null,"abstract":"The requirement for networked multi-core systems is expanding dramatically in many domains such as, aerospace, industry 4.0 and automotive areas. Today's systems that implicate multi-cores, complex architectures and a big variety of applications require well-structured and hierarchical simulation environments. In addition, an efficient and early validation of system requirements during design phase and not during implementation or deployment phases is essential. This has led to a higher demand for simulation tools and environments that can meet the increasing expectations for simulation accuracy, real-time and mixed-criticality support. However, currently there is a gap between the mixed-criticality integration at chip-level and off-chip level, which is a challenge for upcoming mixed-criticality systems with multi-core chips. In this work, a hierarchical simulation environment for mixed-criticality systems based on multi-core chips is introduced. The presented simulation model utilizes criticality-aware interfaces and gateways throughout the different simulated system levels, and successfully combines different simulation tools for the scope of the simulated case realization. In addition, an avionic use-case is presented to validate the presented simulation environment.","PeriodicalId":236091,"journal":{"name":"2018 IEEE 13th International Symposium on Industrial Embedded Systems (SIES)","volume":"998 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116235457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

[Copyright notice] (版权)

2018 IEEE 13th International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2018-06-01 DOI: 10.1109/sies.2018.8442091

引用次数: 0

High Availability in Cyber-physical Systems by Self-determined Virtual Machine Replication 基于自定虚拟机复制的信息物理系统高可用性

2018 IEEE 13th International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2018-06-01 DOI: 10.1109/SIES.2018.8442105

B. Jablkowski, Michael Mueller, O. Spinczyk

{"title":"High Availability in Cyber-physical Systems by Self-determined Virtual Machine Replication","authors":"B. Jablkowski, Michael Mueller, O. Spinczyk","doi":"10.1109/SIES.2018.8442105","DOIUrl":"https://doi.org/10.1109/SIES.2018.8442105","url":null,"abstract":"Present approaches to high availability via virtual machine replication either rely on parallel VM-execution combined with a voting mechanism or periodically transfer state modifications to an inactive backup VM. While redundant execution is expensive in terms of CPU load, periodic checkpointing leads to higher network load and the response times of protected VMs increase and get more jitter. Both alternatives are unacceptable in domains with resource constraints and realtime requirements such as cyber-physical systems. In this work we present a “self-determined” virtual machine replication model for high availability solutions that avoids the drawbacks of both established techniques at the cost of transparency. We argue that for some emerging application domains, such as cyber-physical systems, our model is more suitable. Results show that high availability via self-determined replication can reduce response latencies by an order of magnitude when compared with its periodic counterpart. Especially when used in combination with a lightweight unikernel as guest OS, the overhead of high availability becomes acceptable, even for resource-constrained cyber-physical systems.","PeriodicalId":236091,"journal":{"name":"2018 IEEE 13th International Symposium on Industrial Embedded Systems (SIES)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128628976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Interoperability Between DSRC and LTE for VANETs 用于vanet的DSRC和LTE之间的互操作性

2018 IEEE 13th International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2018-06-01 DOI: 10.1109/SIES.2018.8442086

Heather King, K. Nolan, Mark Y. Kelly

引用次数: 14