2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)最新文献_第2页

The role of photons in cryptanalysis 光子在密码分析中的作用

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2014-02-20 DOI: 10.1109/ASPDAC.2014.6742985

Juliane Krämer, M. Kasper, Jean-Pierre Seifert

引用次数: 6

Scattered refresh: An alternative refresh mechanism to reduce refresh cycle time 分散刷新:减少刷新周期时间的另一种刷新机制

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2014-02-20 DOI: 10.1109/ASPDAC.2014.6742956

T. V. Kalyan, Ravi Kasha, M. Mutyam

引用次数: 6

Semi-analytical current source modeling of FinFET devices operating in near/sub-threshold regime with independent gate control and considering process variation 具有独立栅极控制并考虑工艺变化的近/亚阈值状态下FinFET器件的半解析电流源建模

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2014-02-20 DOI: 10.1109/ASPDAC.2014.6742884

Tiansong Cui, Yanzhi Wang, X. Lin, Shahin Nazarian, Massoud Pedram

{"title":"Semi-analytical current source modeling of FinFET devices operating in near/sub-threshold regime with independent gate control and considering process variation","authors":"Tiansong Cui, Yanzhi Wang, X. Lin, Shahin Nazarian, Massoud Pedram","doi":"10.1109/ASPDAC.2014.6742884","DOIUrl":"https://doi.org/10.1109/ASPDAC.2014.6742884","url":null,"abstract":"Operating circuits in the near/sub-threshold regime can lower the circuit energy consumption at the expense of lowering the circuit speed. In addition near/sub-threshold can result in higher sensitivity to process-induced variations and transient noise. FinFETs have been proposed as an alternative to planar CMOS devices in sub-20nm CMOS technology nodes due to their more effective channel control, steep sub-threshold slope, high ON/OFF current ratio, low power consumption, and so on. Characteristics of FinFETs operating in the near/sub-threshold regime make it difficult to verify the timing of a circuit using conventional statistical static timing analysis (SSTA) techniques. Current source modeling (CSM) methods, which have been proposed to increase the accuracy of timing analysis in dealing with arbitrary shapes of the input signal waveforms, are the appropriate solution for performing SSTA on FinFET-based circuits. This paper thus extends the CSM to such circuits, operating in the near/sub-threshold voltage regime. In particular, FinFET devices with independent gate control and subject to process variations are modelled. The key idea of the proposed CSM approach is to combine non-linear analytical models and low-dimensional CSM lookup tables to simultaneously achieve high modeling accuracy and low time/space complexity.","PeriodicalId":234635,"journal":{"name":"2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114372696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Symbolic computation of SNR for variational analysis of sigma-delta modulator 调制器变分分析中信噪比的符号计算

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2014-02-20 DOI: 10.1109/ASPDAC.2014.6742931

J. Cheng, G. Shi

引用次数: 5

DPA: A data pattern aware error prevention technique for NAND flash lifetime extension DPA:一种数据模式感知的NAND闪存寿命延长错误预防技术

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2014-02-20 DOI: 10.1109/ASPDAC.2014.6742955

Jie Guo, Zhijie Chen, Danghui Wang, Z. Shao, Yiran Chen

引用次数: 29

Advanced technologies for brain-inspired computing 大脑启发计算的先进技术

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2014-02-20 DOI: 10.1109/ASPDAC.2014.6742951

F. Clermidy, R. Héliot, A. Valentian, C. Gamrat, O. Bichler, M. Duranton, B. Belhadj, O. Temam

引用次数: 18

A low-latency asynchronous interconnection network with early arbitration resolution 具有早期仲裁决议的低延迟异步互连网络

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2014-02-20 DOI: 10.1109/ASPDAC.2014.6742911

Georgios Faldamis, Weiwei Jiang, Gennette Gill, S. Nowick

{"title":"A low-latency asynchronous interconnection network with early arbitration resolution","authors":"Georgios Faldamis, Weiwei Jiang, Gennette Gill, S. Nowick","doi":"10.1109/ASPDAC.2014.6742911","DOIUrl":"https://doi.org/10.1109/ASPDAC.2014.6742911","url":null,"abstract":"A new asynchronous arbitration node is introduced for use as a building block in an asynchronous interconnection network. The target network topology is a variant Mesh-of-Trees (MoT), combining a binary fan-out (i.e. routing) network and a binary fan-in (i.e. arbitration) network, which is becoming widely used for multi-core shared-memory interfaces. The two key features are: (i) each fan-in node can resolve its arbitration and pre-allocate the corresponding input channel, before the actual data arrives; and (ii) a lightweight shadow monitoring network fast forwards information as soon as data enters the network without synchronization to a fixed-rate clock, notifying each fan-in node on its path to enable the early arbitration. Simulations of the new arbitration node, using IBM 90nm technology and an ARM standard cell library, indicate latency reductions up to 54.4% over prior designs, while maintaining roughly comparable throughput. Network-level simulations were then performed on eight diverse synthetic benchmarks, comparing the new approach (\"early arbitration\") with two earlier alternative asynchronous MoT networks (\"baseline\" and \"predictive\"), using a mix of random and deterministic traffic. Considerable improvements in system latency were obtained on all benchmarks, ranging from 13.0% to 38.7%, with especially strong benefits for the two most adversarial benchmarks.","PeriodicalId":234635,"journal":{"name":"2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126930535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Optimal SWAP gate insertion for nearest neighbor quantum circuits 最近邻量子电路的最佳SWAP门插入

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2014-02-20 DOI: 10.1109/ASPDAC.2014.6742939

R. Wille, Aaron Lye, R. Drechsler

引用次数: 71

EUV-CDA: Pattern shift aware critical density analysis for EUV mask layouts EUV- cda:模式移位感知的EUV掩模布局临界密度分析

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2014-02-20 DOI: 10.1109/ASPDAC.2014.6742882

A. A. Kagalwalla, Michale Lam, K. Adam, Puneet Gupta

引用次数: 3

Hybrid CMOS/magnetic Process Design Kit and SOT-based non-volatile standard cell architectures 混合CMOS/磁性工艺设计套件和基于sot的非易失性标准电池架构

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2014-02-20 DOI: 10.1109/ASPDAC.2014.6742971

G. D. Pendina, K. Jabeur, G. Prenat

引用次数: 4