2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)最新文献

Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors 基于微处理器能量表征和代码分析的细粒度功率门控设计与控制方法

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2014-03-27 DOI: 10.1109/ASPDAC.2014.6742995

K. Usami, M. Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui, Weihan Wang, H. Amano, Hiroaki Kobayashi, Ryuichi Sakamoto, M. Namiki, Masaaki Kondo, Hiroshi Nakamura

引用次数: 9

BOB-router: A new buffering-aware global router with over-the-block routing resources optimization BOB-router:一种新的具有缓冲意识的全局路由器，具有跨块路由资源优化功能

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2014-03-27 DOI: 10.1109/ASPDAC.2014.6742943

Yilin Zhang, Salim Chowdhury, D. Pan

{"title":"BOB-router: A new buffering-aware global router with over-the-block routing resources optimization","authors":"Yilin Zhang, Salim Chowdhury, D. Pan","doi":"10.1109/ASPDAC.2014.6742943","DOIUrl":"https://doi.org/10.1109/ASPDAC.2014.6742943","url":null,"abstract":"In this paper, we propose a new global router, BOB-Router, endowed with the ability to use over-the-block routing resources to the greatest extent in addition to traditional routing concepts of minimizing wirelength, via count and overflow. In previous global routing formulations, the routing resources over the IP blocks were either dealt as routing blockages leading to a significant waste, or simply treated in the same way as outside-the-block routing resources, which violates the slew constraints and thus fail buffering. Utilizing over-the-block routing resources could dramatically improve the routing solution, yet requires special attention, since the slew, affected by different RC on different metal layers, must be constrained by buffering and is easily violated. Moreover, even all nets are slew-legalized, the routing solution could still suffer from heavy congestion problem. For the first time, BOB-Router tries to solve the over-the-block global routing problem through minimizing overflows, wirelength and via count simultaneously without violating slew constraints. BOB-Router generates a slew-legalized initial solution followed by a Lagrangian-multiplier-based pricing phase and RC-constrained A* search to help explore new buffering-aware topologies on all metal layers. Our experimental results show that BOB-Router completely satisfies the slew constraints and significantly outperforms the obstacle-avoiding global routers in terms of wirelength, via count and overflows.","PeriodicalId":234635,"journal":{"name":"2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116140250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

7.3 Gb/s universal BCH encoder and decoder for SSD controllers 7.3 Gb/s通用BCH编解码器，用于SSD控制器

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2014-02-20 DOI: 10.1109/ASPDAC.2014.6742862

Hoyoung Yoo, Youngjoo Lee, I. Park

引用次数: 18

Variation-aware voltage island formation for power efficient near-threshold manycore architectures 功率效率近阈值多核架构的变化感知电压岛形成

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2014-02-20 DOI: 10.1109/ASPDAC.2014.6742907

Ioannis S. Stamelakos, S. Xydis, G. Palermo, C. Silvano

{"title":"Variation-aware voltage island formation for power efficient near-threshold manycore architectures","authors":"Ioannis S. Stamelakos, S. Xydis, G. Palermo, C. Silvano","doi":"10.1109/ASPDAC.2014.6742907","DOIUrl":"https://doi.org/10.1109/ASPDAC.2014.6742907","url":null,"abstract":"The power-wall problem and its dual utilization-wall problem are considered among the main barriers to feasible/efficient scaling in the manycore era. Several researchers have proposed the usage of aggressive voltage scaling techniques at the near-threshold voltage region, promising significant improvements in power efficiency at the expense of reduced performance values and higher sensitivity to process parametric variations. In this paper, we introduce a variability-aware framework for exploring the potential power-efficiency of the Near Threshold Computing (NTC) under performance constraints. We propose and analyze the usage of fine-grained voltage islands to cope with the increased effect of variability problem in the NTC region. For the considered workloads, we found that the power impact of fine-grained voltage islands formation can be up to 35% for a 128-core chip operating at NTC region, while the adoption of a variability aware technique can bring to a power reduction of up to 43% with respect to a variability unaware technique. Finally, we show that voltage regulator's complexity, in terms of voltage quantization levels, has a very low effect on the power efficiency at NTC, making in that way the usage of voltage islands a feasible solution for copying with variability1.","PeriodicalId":234635,"journal":{"name":"2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121378727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Efficient parallel GPU algorithms for BDD manipulation BDD操作的高效并行GPU算法

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2014-02-20 DOI: 10.1109/ASPDAC.2014.6742980

M. Velev, Ping Gao

引用次数: 9

A fast and provably bounded failure analysis of memory circuits in high dimensions 高维存储电路的快速、可证明的有界失效分析

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2014-02-20 DOI: 10.1109/ASPDAC.2014.6742928

Wei Wu, Fang Gong, Gengsheng Chen, Lei He

{"title":"A fast and provably bounded failure analysis of memory circuits in high dimensions","authors":"Wei Wu, Fang Gong, Gengsheng Chen, Lei He","doi":"10.1109/ASPDAC.2014.6742928","DOIUrl":"https://doi.org/10.1109/ASPDAC.2014.6742928","url":null,"abstract":"Memory circuits have become important components in today's IC designs which demands extremely high integration density and reliability under process variations. The most challenging task is how to accurately estimate the extremely small failure probability of memory circuits where the circuit failure is a “rare event”. Classic importance sampling has been widely recognized to be inaccurate and unreliable in high dimensions. To address this issue, we propose a fast statistical analysis to estimate the probability of rare events in high dimensions and prove that the estimation is always bounded. This methodology has been successfully applied to the failure analysis of memory circuits with hundreds of variables, which was considered to be very intractable before. To the best of our knowledge, this is the first work that successfully solves high dimensional “rare event” problems without using expensive Monte Carlo and classic importance sampling methods. Experiments on a 54-dimensional SRAM cell circuit show that the proposed approach achieves 1150x speedup over Monte Carlo without compromising any accuracy. It also outperforms the classification based method (e.g., Statistical Blockade) by 204x and existing importance sampling method (e.g., Spherical Sampling) by 5x. On another 117-dimension circuit, the proposed approach yields 364x speedup over Monte Carlo while existing importance sampling methods completely fail to provide reasonable accuracy.","PeriodicalId":234635,"journal":{"name":"2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125522101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24

Energy efficient in-memory machine learning for data intensive image-processing by non-volatile domain-wall memory 通过非易失性域壁存储器实现数据密集型图像处理的高能效内存机器学习

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2014-02-20 DOI: 10.1109/ASPDAC.2014.6742888

Hao Yu, Yuhao Wang, Shuai Chen, Wei Fei, Chuliang Weng, Junfeng Zhao, Z. Wei

引用次数: 26

A transaction-oriented UVM-based library for verification of analog behavior 一个面向事务的基于uvm的库，用于验证模拟行为

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2014-02-20 DOI: 10.1109/ASPDAC.2014.6742989

Alexander W. Rath, Volkan Esen, W. Ecker

引用次数: 14

SDG2KPN: System Dependency Graph to function-level KPN generation of legacy code for MPSoCs SDG2KPN: mpsoc遗留代码的功能级KPN生成的系统依赖图

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2014-02-20 DOI: 10.1109/ASPDAC.2014.6742901

Jude Angelo Ambrose, Jorgen Peddersen, S. Parameswaran, Alvin Labios, Yusuke Yachide

{"title":"SDG2KPN: System Dependency Graph to function-level KPN generation of legacy code for MPSoCs","authors":"Jude Angelo Ambrose, Jorgen Peddersen, S. Parameswaran, Alvin Labios, Yusuke Yachide","doi":"10.1109/ASPDAC.2014.6742901","DOIUrl":"https://doi.org/10.1109/ASPDAC.2014.6742901","url":null,"abstract":"The Multiprocessor System-on-Chip (MPSoC) paradigm as a viable implementation platform for parallel processing has expanded to encompass embedded devices. The ability to execute code in parallel gives MPSoCs the potential to achieve high performance with low power consumption. In order for sequential legacy code to take advantage of the MPSoC design paradigm, it must first be partitioned into data flow graphs (such as Kahn Process Networks - KPNs) to ensure the data elements can be correctly passed between the separate processing elements that operate on them. Existing techniques are inadequate for use in complex legacy code. This paper proposes SDG2KPN, a System Dependency Graph to KPN conversion methodology targeting the conversion of legacy code. By creating KPNs at the granularity of the function-/procedure-level, SDG2KPN is the first of its kind to support shared and global variables as well as many more program patterns/application types. We also provide a design flow which allows the creation of MPSoC systems utilizing the produced KPNs. We demonstrate the applicability of our approach by retargeting several sequential applications to the Tensilica MPSoC framework. Our system parallelized AES, an application of 950 lines, in 4.8 seconds, while H.264, of 57896 lines, took 164.9 seconds to parallelize.","PeriodicalId":234635,"journal":{"name":"2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121620207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

An overview of spin-based integrated circuits 基于自旋的集成电路概述

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2014-02-20 DOI: 10.1109/ASPDAC.2014.6742969

Wang-Cheng Kang, Weisheng Zhao, Zhaohao Wang, Jacques-Olivier Klein, Yue Zhang, Djaafar Chabi, Youguang Zhang, D. Ravelosona, C. Chappert

引用次数: 28