发布求助
文献互助 智能选刊 最新文献

2008 IEEE International Conference on Electron Devices and Solid-State Circuits最新文献

筛选
英文 中文
An efficiency-enhanced low dropout Linear HB LED driver for automotive application 一种用于汽车应用的效率增强的低差线性HB LED驱动器
2008 IEEE International Conference on Electron Devices and Solid-State Circuits Pub Date : 2008-12-01 DOI: 10.1109/EDSSC.2008.4760666
Lin Ying-yan, Zhang Jing, Zou Xue-cheng, Li Wei
{"title":"An efficiency-enhanced low dropout Linear HB LED driver for automotive application","authors":"Lin Ying-yan, Zhang Jing, Zou Xue-cheng, Li Wei","doi":"10.1109/EDSSC.2008.4760666","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760666","url":null,"abstract":"An efficiency-enhanced linear LED driver, which operates with a wide input voltage range (6.3 V~32 V) and is able to provide output current up to 350 mA with accuracy of plusmn3%, is presented in this paper. To improve driving efficiency, an operational amplifier is exploited to lower current-sense voltage while PMOS pass element with elaborate metal layout pattern is used to reduce dropout loss. Besides, a 5 V regulated voltage is obtained from the wide range input voltage to supply some modules in the driver so as to further diminish power dissipation of the driver. The proposed driver has been fabricated on a 0.5 mum BCD process occupying 1.4 mm times 1.8 mm area. Post-simulation results show that the proposed scheme driving three HB-LEDs in series can achieve the maximum efficiency of 91.04% at ILOAD=350 mA, which is enhanced by 7.2% compared with that of the typical linear LED driver under the same condition. The dropout voltage is 450 mV when the load current is 350 mA. Besides, it is able to recover within 99 mus.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122358533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
High sensitivity pH sensor using AlXGa1-XN/GaN HEMT heterostructure design 高灵敏度pH传感器采用AlXGa1-XN/GaN HEMT异质结构设计
2008 IEEE International Conference on Electron Devices and Solid-State Circuits Pub Date : 2008-12-01 DOI: 10.1109/EDSSC.2008.4760643
Hsin-Shun Huang, Chao-Wei Lin, H. Chiu
{"title":"High sensitivity pH sensor using AlXGa1-XN/GaN HEMT heterostructure design","authors":"Hsin-Shun Huang, Chao-Wei Lin, H. Chiu","doi":"10.1109/EDSSC.2008.4760643","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760643","url":null,"abstract":"Gateless AlGaN/GaN high electron mobility transistors (HEMTs) has some advantages include rapid response, low noise, and superior sensitivity. In different Al content, the Al<sub>0.3</sub>Ga<sub>0.7</sub>N has the excellent performance among Al<sub>0.17</sub>Ga<sub>0.83</sub>N and Al<sub>0.25</sub>Ga<sub>0.75</sub>N, and the performance can be achieved about -0.923 mA/mm-pH during pH 4-10, and -2.24 mA/mm-pH during pH 7-8. The result indicates that the better performance of Al<sub>0.3</sub>Ga<sub>0.7</sub>N can be applied in high sensitivity pH sensor. Using the characteristic and modifying by different gate oxide, there are many application in the technology of medical for detecting the disease.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127121847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Low power wireless receiver in CMOS mixed-signal for bio-telemetry implantable system 用于生物遥测植入系统的CMOS混合信号低功耗无线接收机
2008 IEEE International Conference on Electron Devices and Solid-State Circuits Pub Date : 2008-12-01 DOI: 10.1109/EDSSC.2008.4760665
L. Hongge, Youguang Zhang
{"title":"Low power wireless receiver in CMOS mixed-signal for bio-telemetry implantable system","authors":"L. Hongge, Youguang Zhang","doi":"10.1109/EDSSC.2008.4760665","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760665","url":null,"abstract":"A novel mixed-signal interlace is presented for implantable interlace receiver consists of an analog front-end and a digital processing circuit. The analog circuit consists of mainly an amplifier, an ASK demodulator, a clock extraction and a power recovery. In this paper, the amplifier and the ASK demodulator are described and provided without the capacitor and the resistor, fully integrated, low-power circuit. We also developed the processing circuit with the digital technology, so that implementing the correct synchronous signal. The carrier frequency of the circuit is applied in the 10 MHz range, the data rates up to IM bits are supported, suitable for complex implantable microsystem such as the brain neural mutual interface and so on. Low-power and high-performance implantable interface using a CMOS technology has been designed, fabricated and verified. All of circuits were implemented in a standard 0.18-mum CMOS technology. The power dissipation of the mixed-signal micros stem is verified to be less than 2.75 mW @ 1.8 V.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127907484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Effects of gate length on the performance of a top gate silicon nanowire on insulator (SOI) transistor 栅极长度对绝缘体(SOI)晶体管顶栅硅纳米线性能的影响
2008 IEEE International Conference on Electron Devices and Solid-State Circuits Pub Date : 2008-12-01 DOI: 10.1109/EDSSC.2008.4760708
S. Bhowmick, R. Sajjad, Q. Khosru
{"title":"Effects of gate length on the performance of a top gate silicon nanowire on insulator (SOI) transistor","authors":"S. Bhowmick, R. Sajjad, Q. Khosru","doi":"10.1109/EDSSC.2008.4760708","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760708","url":null,"abstract":"The effects of gate length Lg on the performance of a top gate silicon nanowire on insulator transistor are studied using three dimensional quantum simulation. From the study it is found that the inverse subthreshold slope and on/off current ratio are very sensitive to gate length. Significant improvement in subthreshold slope and on/off current ratio can be achieved using relatively longer gate with thin gate oxide. This improvement in the subthreshold region is due to better control of channel potential with longer gate. As a result of that the tunneling current through the conduction band is significantly suppressed in the subthreshold regime and there is an improvement in the subthreshold slope and on/off current ratio. Performance metrics such as transconductance gm, intrinsic switching delay tauS and unity current gain frequency fT of the device are also calculated and it is found that the on state performance of the device degrades with longer gate as all three parameters degrade with increased gate length.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129148207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Assessment of novel phase change memory programming techniques 新型相变存储器编程技术的评估
2008 IEEE International Conference on Electron Devices and Solid-State Circuits Pub Date : 2008-12-01 DOI: 10.1109/EDSSC.2008.4760662
Yi-Bo Liao, Jun-Tin Lin, M. Chiang, W. Hsu
{"title":"Assessment of novel phase change memory programming techniques","authors":"Yi-Bo Liao, Jun-Tin Lin, M. Chiang, W. Hsu","doi":"10.1109/EDSSC.2008.4760662","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760662","url":null,"abstract":"In this paper, we present novel phase change memory programming techniques achieving low power operation without compromising performance by using proper pulsing schemes. By applying continuous current pulses at a fixed frequency or with the same pulse magnitude, binary data are successfully written into memory cells. The proposed programming techniques can be implemented with more flexible or simplified circuitry since a single current level is shown to be sufficient for write operations of both set and reset states.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123537314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design and analysis of 600 V power MOSFET with multiple field limiting ring 600 V功率多场限制环MOSFET的设计与分析
2008 IEEE International Conference on Electron Devices and Solid-State Circuits Pub Date : 2008-12-01 DOI: 10.1109/EDSSC.2008.4760732
Wing-Shan Tam, O. Wong, C. Kok, H. Wong
{"title":"Design and analysis of 600 V power MOSFET with multiple field limiting ring","authors":"Wing-Shan Tam, O. Wong, C. Kok, H. Wong","doi":"10.1109/EDSSC.2008.4760732","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760732","url":null,"abstract":"This paper presents an analytical model and optimization process for multiple floating field limiting ring (MFFLR) structure pursuing high voltage blocking capability with evenly distributed electric field. The three-dimensional (3-D) model considers both the sphere-junction effect and cylindrical-junction effect, which formulates an accurate 3-D model for optimization. Design example obtained by the proposed method is examined with MEDICI simulation and consistent results are observed.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115838281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Nested miller active-capacitor frequency compensation for low-power three-stage amplifiers 小功率三级放大器的嵌套米勒有源电容频率补偿
2008 IEEE International Conference on Electron Devices and Solid-State Circuits Pub Date : 2008-12-01 DOI: 10.1109/EDSSC.2008.4760637
H.F. Ma, F. Zhou
{"title":"Nested miller active-capacitor frequency compensation for low-power three-stage amplifiers","authors":"H.F. Ma, F. Zhou","doi":"10.1109/EDSSC.2008.4760637","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760637","url":null,"abstract":"A new frequency compensation technique for low-power, area-efficient multistage amplifiers is introduced in this work. By utilizing active capacitors to realize the compensation network in a nested way, two inverting gain stages can be used as the second and third gain-stages. The proposed scheme reaches better bandwidth-to-power and slew-rate-to-power performances comparing to the ever published works. Implemented in a standard 0.35 um CMOS technology, the proposed three-stage amplifier achieves 112-dB DC gain, 1.7-M GBW, 47deg phase margin and 1.95-V/mus average slew rate under a 500 pF capacitive load. All of these are realized with only 38 muW power consumption under a 2-V power supply and with very small compensation capacitors.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"292 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116359879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A global continuous channel potential solution for double-gate MOSFETs 双栅mosfet的全球连续通道电位解决方案
2008 IEEE International Conference on Electron Devices and Solid-State Circuits Pub Date : 2008-12-01 DOI: 10.1109/EDSSC.2008.4760671
Feng Liu, Jin He, Jian Zhang, M. Chan
{"title":"A global continuous channel potential solution for double-gate MOSFETs","authors":"Feng Liu, Jin He, Jian Zhang, M. Chan","doi":"10.1109/EDSSC.2008.4760671","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760671","url":null,"abstract":"A global continuous channel potential solution is proposed for the modeling of symmetric double-gate (DG) MOSFETs. To obtain the channel potential, from accumulation to inversion regions, 1-D Poissonpsilas equation in the silicon film of the DG MOSFETs is solved physically. The extensive comparisons between the calculated results and numerical simulations illustrate that the analytical solution is not only accurate and continuous in the whole operation regime of DG MOSFETs, but also valid to various doping concentrations and geometrical sizes, without any fitting parameter.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124844886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A high-sensitivity transimpedance amplifier for 1.25-Gbps GE-PON system 一种用于1.25 gbps GE-PON系统的高灵敏度跨阻放大器
2008 IEEE International Conference on Electron Devices and Solid-State Circuits Pub Date : 2008-12-01 DOI: 10.1109/EDSSC.2008.4760748
J. Chen, J. Xu, D.G. Zhong, C.X. Li
{"title":"A high-sensitivity transimpedance amplifier for 1.25-Gbps GE-PON system","authors":"J. Chen, J. Xu, D.G. Zhong, C.X. Li","doi":"10.1109/EDSSC.2008.4760748","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760748","url":null,"abstract":"A high-sensitivity transimpedance amplifier (TIA) for Gigabit Ethernet passive optical network (GE-PON) system is designed in 0.35-mum BiCMOS technology. This amplifier has a 1.37-GHz bandwidth and 55 k transimpedance gain. Also it exhibits a high sensitivity of -31.1 dBm at 1.25 Gbps with a PIN-PD instead of APD, which provides a low-cost and high-performance FTTH solution.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"305 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132756475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Investigation of problems in JEDEC HBM ESD test standard JEDEC HBM静电测试标准中存在问题的探讨
2008 IEEE International Conference on Electron Devices and Solid-State Circuits Pub Date : 2008-12-01 DOI: 10.1109/EDSSC.2008.4760646
M. Huo, Yan Han, Qi Liu, B. Song, Qingrong Ma, Kehan Zhu, Y. Shen, Xiaoyang Du, S. Dong
{"title":"Investigation of problems in JEDEC HBM ESD test standard","authors":"M. Huo, Yan Han, Qi Liu, B. Song, Qingrong Ma, Kehan Zhu, Y. Shen, Xiaoyang Du, S. Dong","doi":"10.1109/EDSSC.2008.4760646","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760646","url":null,"abstract":"Sufficient emphasis need be applied to current EIA/JEDEC Human-Body Model (HBM) Electrostatic Discharge (ESD) test standard, which does not define the start and step test voltages. Some measurement begins from several kilo-volts, which makes it ignored that ESD protection devices might fail under low voltage stresses. A Gate-Grounded NMOS (GGNMOS) structure with an NWell-ballast resistor connecting its drain and PAD is investigated for HBM ESD sustaining levels in this paper. When tested with a Zapmaster of HBM model starting from 1 kilo-volt, the withstand voltage exceeds 8 kilo-volts, whereas the structure failed at 350 volts when the test initiates from 50 volts. The test results from a Transmission-Line Pulsing (TLP) system validate the phenomenon. The reason of the failure is also analyzed and proved with OBIRCH Failure Analysis (FA) results. To overcome this general issue, a suggestion for improving present HBM ESD testing standards for industry application is proposed.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129891724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信
小红书