K.H. Lee, P. Chang, S. Chang, Y. Wang, C. Kuo, S.L. Wu
{"title":"GaN Schottky barrier photodetectors with multi-MgN/GaN buffer","authors":"K.H. Lee, P. Chang, S. Chang, Y. Wang, C. Kuo, S.L. Wu","doi":"10.1109/EDSSC.2008.4760683","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760683","url":null,"abstract":"GaN Schottky barrier photodetectors (PDs) separately prepared with a conventional single low-temperature (LT) GaN buffer layer and a multi-MgN/GaN buffer layer were both fabricated. It was found that we could reduce threading dislocation (TD) density and thus improve crystal quality of the GaN PDs by using the multi-MgN/GaN buffer layer. With a 2 V reverse bias, it was found that the reverse leakage currents measured from PDs with single LT GaN buffer layer and that with multi-MgN/GaN buffer layer were 4.57times10-6 and 1.44times10-12 A, respectively. It was also found that we could use the multi-MgN/GaN buffer layer to suppress photoconductive gain, enhance UV-to-visible rejection ratio, reduce noise level and enhance the detectivity.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122871468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Ollier, P. Andreucci, L. Duraffourg, É. Colinet, C. Durand, F. Casset, T. Ernst, S. Hentz, S. Labarthe, C. Marcoux, V. Nguyen, D. Renaud, E. Mile, P. Renaux, D. Mercier, P. Robert, P. Ancey, L. Bouchaillot
{"title":"NEMS based on top-down technologies: from stand-alone NEMS to VLSI NEMS & NEMS-CMOS integration","authors":"E. Ollier, P. Andreucci, L. Duraffourg, É. Colinet, C. Durand, F. Casset, T. Ernst, S. Hentz, S. Labarthe, C. Marcoux, V. Nguyen, D. Renaud, E. Mile, P. Renaux, D. Mercier, P. Robert, P. Ancey, L. Bouchaillot","doi":"10.1109/EDSSC.2008.4760714","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760714","url":null,"abstract":"This paper reviews some recent advances related to NEMS based on top-down technologies: from stand-alone NEMS to VLSI NEMS and NEMS-CMOS integration.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124547960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of dual-gigabit transceiver for fibre channel FC-1 layer","authors":"Guicai Sun, Dunshan Yu","doi":"10.1109/EDSSC.2008.4760719","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760719","url":null,"abstract":"Fibre channel is a gigabit-speed network technology which dominates todaypsilas high-end storage network market. Its topology consists of several layers. This paper presents a transceiver design with FS-HSPI compliant interface used for Fibre Channel Transmission Protocol Layer.. or FC-1 layer. Optimized 8B/10B encoder/decoder architecture and parallel CRC checking algorithm are used in order to satisfy high-speed requirements and ensure reliability during transmission. By providing DDR/SDR interface, the transceiver can support both 1.0625 Gbit/s and 2.125 Gbit/s transmission rate. FIFO buffering and clock correction technique are used to accommodate the rate difference between recovered clock and receiver clock. Synthesis results using Synopsys Design Compiler in SMIC 0.18 um technology shows our design can reach the required baud rate.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128625223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Chung, T. Tsai, Chun-Rong Lin, Shin-Zong Lu, H. Lin, J. Tsai, Chin-Chen Chu
{"title":"Uniform Fe3O4- pyrrolidone nanofiber thin film","authors":"M. Chung, T. Tsai, Chun-Rong Lin, Shin-Zong Lu, H. Lin, J. Tsai, Chin-Chen Chu","doi":"10.1109/EDSSC.2008.4760725","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760725","url":null,"abstract":"Magnetite (Fe3O4) nanoparticles with diameters ranging from 6-8 nm were produced with polyol process, and mixed with pyrrolidone to serve as a precursor for electrospinning process. A uniform nanofiber film were produce with such solution, which exhibits improved quality over previous attempt. Such nanofiber thin film can be used in sensors.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116722464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A full on-chip low-dropout linear regulator with enhanced line, load regulation","authors":"H.F. Ma, F. Zhou","doi":"10.1109/EDSSC.2008.4760634","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760634","url":null,"abstract":"A novel full on-chip (capacitor-less) low-dropout linear regulator is introduced in this paper. The main feature of the proposed LDO is its ability to be stable in the full-output-current range while still has good line and load regulations as well as improved transient response. This is achieved by using an advanced compensation network along with an adaptive-gain PMOS pass device. The post-layout simulations have revealed the advantageous performances of the LDO in all process corners. These include 3 uV/mA load regulation, 200 uV/V line regulation as well as 200 mV output voltage variation during load transient (the worst case). They are achieved in the condition of 0-100 mA output current capability, 200 mV dropout voltage and 54 uA no-load current consumption under a 2V supply.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"210 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115217125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Polysilicon nanowire chemical sensor based on CMOS standard process","authors":"C.-W. Huang, S.-C. Hsu, C.-T. Lin","doi":"10.1109/EDSSC.2008.4760705","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760705","url":null,"abstract":"Based on the improvements of the lithography technology, the dimension of the device has decreased to nanometer. On the other hand, silicon nanowire has been proposed to detect proteins, DNA, and ions etc. In general, the silicon nanowires are made either by CVD (chemical vapor deposition) or by silicon on insulator (SOI) fabrication process. The former has trouble in electrodes arranging and the latter suffers from more expensive than standard semiconductor process. In this work, we announced CMOS compatible technique which is used to develop polysilicon nanowire field effect transistor as a chemical sensor with low cost and high fidelity to pave the way toward system-on-chip design.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114433033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An energy-efficient ASIC with real-time work-on-demand for wireless body sensor network","authors":"Zhihua Wang, Xiaoyu Zhang, Xinkai Chen, Lingwei Zhang, Hanjun Jiang","doi":"10.1109/EDSSC.2008.4760681","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760681","url":null,"abstract":"This paper presents an energy efficient ASIC design with the capability of real-time work-on-demand, targeting on the applications of wireless body sensor network (WBSN), especially on those for medical and heath purposes. Application specific requirements have been reviewed. A novel type of sensor node architecture is proposed with a hybrid of active/passive transceivers. The passive RF receiver with zero standby current gives the WBSN nodes the real capability of work-on-demand which is not allowed in previous architectures. A power management module with an optimized power mode control scheme has also implemented to provide various supply voltages for the sensor nodes, and in addition this module can provide the sensor nodes a flexible power mode control for the purpose of energy saving. An ultra-low-power MCU which supports the proposed architecture has been integrated in the ASIC, which can perform the functions of media access, signal flow control and networking. The proposed architecture has been verified through FPGA experiments, and the ASIC has been designed and fabricated using a standard 0.18 um CMOS process. The designed ASIC occupies a die area of 2 mm times 2.5 mm. The digital core of this ASIC has 72.8 K equivalent gate counts excluding the memories. A typical WBSN sensor node can be built with this ASIC in together with a commercial RF transceiver, the sensor parts and some other components, and our ASIC can serve as the main control part for such a node.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127830243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A dual band CMOS two-stage variable gain low noise amplifier","authors":"Juan Li, Feng Zhao, Yumei Huang, Zhiliang Hong","doi":"10.1109/EDSSC.2008.4760712","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760712","url":null,"abstract":"A low power CMOS fully-integrated on-chip inductor-less low noise amplifier (LNA) designed for short range devices (SRDs) in 0.25-mum CMOS process is presented. It is working at 315 MHz and 433 MHz. Common gate input topology is adopted to realize wideband impedance matching without tuning. Cross coupled common-gate input technique is adopted to improve the noise performance of conventional common-gate LNA. Two-stage variable gain architecture is used to optimize the gain, noise and linearity simultaneously. The simulated S11 is below -17 dB across the entire band and the minimum noise figure is 2.55 dB when the gain is set to the highest. The LNA provides a gain control range of 36 dB and the simulated IIP3 is -2.7 dBm. The power consumption is 5.5 mW without the output buffer at a 2.5 V supply voltage. The core circuit area is 0.33 mm times 0.18 mm.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122047483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Novel asymmetric MOSFET structures for low power applications","authors":"N. Venkatagirish, R. Jhaveri, A. Tura, J. Woo","doi":"10.1109/EDSSC.2008.4760736","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760736","url":null,"abstract":"As MOSFET is scaled below 90 nm, many daunting challenges arise. Short channel effects (DIBL and VTH roll-off), off-state and gate leakage, parasitic capacitance and resistance severely limit the performance of these transistors. These, in addition to VDD scaling limitation and high sub-threshold swing (>60 mv/dec) give rise to high IOFF and make power dissipation an enormous challenge, especially for low power/low current applications. New device innovations are essential to achieve low IOFF and high gm with high ROUT for digital and analog applications respectively. Towards this end, novel asymmetric Tunneling Source MOSFETs are proposed in this paper. The main feature of these devices is the concept of gate controlled carrier injection through tunneling at the source junction. The tunneling source MOSFETs can be fabricated using conventional CMOS processes. These novel devices have the potential for steep sub-threshold behavior, improved ION/IOFF, high ROUT and gain (gm times ROUT) at low bias currents. They also possess excellent immunity against short channel effects which improves scalability into sub-50 nm regime and makes them an attractive candidate for low power digital and analog operations.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127098291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High-Q VHF micromechanical filters using free-free beam resonators","authors":"C.-J. Li, S.-K. Lin","doi":"10.1109/EDSSC.2008.4760717","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760717","url":null,"abstract":"This paper presents an innovative micromechanical bandpass filter using free-free beam resonators and torsional coupling beams for VHF applications. The rationale for adopting free-free beam resonators is that the free-free beam resonators would experience less anchor loss than a clamped-clamped resonators. ANSYS simulation shows that the proposed free-free beam filter possess less anchor loss. Finally, experimental results demonstrate that the free-free beam filter is feasible at the VHF operation.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132577860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}